NEW

Building an MNIST NPU with FPGA — From RTL to Bit-True Verification

Name: Building an MNIST NPU with FPGA — From RTL to Bit-True Verification
Price: 158400 KRW

Putting a neural network on an FPGA—the phrase is familiar, but few have actually done it. If you want to stay a step ahead in capstone projects, competitions, or graduation projects, you must be able to go beyond just training a model and actually build and prove how those computations run inside a real chip. This course bridges that exact gap between theory and physical hardware. You will complete a neural network accelerator (NPU) for MNIST digit recognition from start to finish—from reading specifications to Python golden models, Verilog RTL design, and FPGA verification. From Conv layers made with line buffers and parallel MACs, through ReLU, MaxPool, and Flatten, to fully connected layers and Argmax—you will integrate nine blocks into a single chip and prove for yourself that "the Python reference and the hardware output do not differ by even a single bit (Bit-True)." I have even included how to overcome those frustrating moments when the simulation runs fine but the results are subtly different. I will guide you through practical know-how that general deep learning textbooks don't cover, such as integer quantization, array axis reordering, and accumulator overflow prevention. I have distilled the trial and error I experienced over years of RISC-V CPU design and FPGA Bit-True verification into this course so that you don't have to repeat them. By the end of the class, you will have a completed hardware project that allows you to say, "I designed and verified it myself."

1 learners are taking this course

Level Intermediate

Course period Unlimited

EdgeChipLab

Artificial Neural Network

Computer Vision(CV)

Verilog HDL

FPGA

verification

Artificial Neural Network

Computer Vision(CV)

Verilog HDL

FPGA

verification

What you will gain after the course

A complete Neural Processing Unit (NPU) project, from specification to RTL and verification, suitable for submission to capstone projects, competitions, and graduation projects.
The entire process of first fixing hardware constraints, training the neural network accordingly, quantizing the weights into integers, and porting them to hardware — the experience of building everything yourself from the training stage, rather than just using weights created by others.
Bit-True verification capability to directly prove that the Python reference and hardware output do not differ by even a single bit — the skill to turn "it seems to work" into "proven to be an exact match"
Design capability to directly implement Conv, ReLU, MaxPool, Flatten, Fully Connected, and Argmax in Verilog RTL (including line buffers, parallel MACs, and accumulators)
Know-how for handling practical pitfalls such as axis order conversion, scale adjustment, and accumulator overflow prevention encountered when converting trained floating-point weights to integers.
System integration experience in integrating and verifying individual blocks into a single chip.
The first step of NPU ISA design to expand fixed accelerators into instruction-based processors

Building neural networks as chips, not software.

From specification to RTL and verification, design an MNIST recognition NPU yourself and prove it down to a single bit.

Have you ever had these concerns?

You've trained models, but no one teaches you how to actually deploy them onto an FPGA. You've worked with Verilog, but you've never completed an entire neural network as a single accelerator. You've chosen "AI Hardware" as your capstone or graduation project topic, but you're at a loss as to where to begin. You converted floating-point weights to integers, and while the simulation runs, the results are strange. You've confirmed that "it seems to work," but you don't know how to prove it's actually correct.

The answer this course provides

This course builds a Neural Processing Unit (NPU) for MNIST digit recognition from scratch, covering everything from reading specifications to Python golden models, hardware-constrained training and integer quantization, Verilog RTL design, and FPGA bit-true verification without skipping a single step.

By the end of the course, you will have a completed hardware project in your hands that can be submitted as-is for capstone projects, competitions, and graduation projects. And you will be able to say, "I trained it, designed it, and verified it myself, down to the very last bit."

The cheat code unique to this course

First, hardware comes first, followed by training. Instead of using weights created by others, you first fix hardware constraints such as bit width and operation order, and then train the neural network yourself to fit those constraints. The Python model becomes the bit-level blueprint for the RTL.

Second, we change "it seems to work" to "it matches exactly." We put Bit-True verification, which proves that the Python integer golden model and the RTL output do not differ by even a single bit, at the forefront. We convey the pitfalls of practical work, including why it is easy to be deceived if only the classes match and why large-scale verification is necessary.

Third, we move from accelerators to processors. It doesn't stop at a single example; we open the path for you to expand a fixed accelerator into an instruction-controlled processor (NPU ISA).

Curriculum at a glance (7 sections · 10 lectures · 7 hours 7 minutes)

Section 1. The Language of Design — How to Read MNIST NPU Specifications
Section 2. Python — Hardware Reference (Golden Model), Training, and Integer Quantization
Section 3. Feature Extraction Circuits — Line Buffers and 4-Channel Parallel MAC
Section 4. Transformation and Decision Circuits — ReLU, MaxPool, Flatten, Fully Connected, and Argmax
Section 5. Integration and Verification — Nine Blocks into One Chip, Proving with Bit-True
Section 6. Expansion — NPU ISA and Mini Compiler
Section 7. Setting Up the Practice Environment — Must Check Before Simulation

Recommended for

This course is recommended for undergraduate students preparing capstone or graduation projects on AI hardware, competition participants in need of standout results, working engineers at design firms looking to expand their expertise into NPUs and AI accelerators, self-motivated hardware engineers seeking the experience of building and verifying that theory books alone cannot provide, and prospective graduate students aiming for a career in NPU design.

Prerequisites

Basic knowledge of Verilog HDL and digital logic design is sufficient. For Python, being able to read and run code is enough, and you don't need to know deep learning theory — neural network operations are explained from scratch from a hardware perspective. Even if you are new to FPGA tools, Section 7 provides guidance on setting up the environment.

Recommended for
these people

Who is this course right for?

Professional hardware engineers currently working at semiconductor or design firms who want to expand their capabilities into AI accelerator and NPU design — those who are familiar with RTL design but need experience in completing and verifying a neural network as a full accelerator.
Self-development-oriented engineers who want to steadily improve their skills even amidst busy work — those who want practical projects that go beyond theory books, where they build and prove results with Bit-True.
Undergraduate students majoring in electronics, electrical engineering, or semiconductors who have chosen "AI Hardware" as their capstone or graduation project topic, but feel lost on how to convert neural networks to RTL and implement them on an FPGA.
Participants in competitions who need results that stand out — those who want to showcase an "NPU designed personally and proven with Bit-True" rather than just model training.
Prospective graduate students aiming for a career in NPU/AI accelerator design who need implementation and verification experience rather than just theory.

Need to know before starting?

This course is intended for those who have a basic understanding of Verilog HDL and digital logic design.
Basic Python syntax is sufficient as long as you can read and execute the golden model code.
Experience with FPGA simulation tools is a plus.

Hello
This is EdgeChipLab

As a current university professor, I have incorporated 30 years of system semiconductor expertise.

This is a practical curriculum directly designed and verified by a professor of semiconductor engineering, whose career spans from a system semiconductor researcher at Samsung Electronics' DS Division to Director of UK and German subsidiaries and Head of the System LSI Marketing & Sales Group.

Level up your engineering capabilities by going beyond theory to actual hardware implementation.

There are realms that scattered, fragmentary knowledge alone can never reach. Students will not merely be users of pre-built black-box IPs; they will design NPUs and CPUs, integrate peripherals, and ultimately evolve into system architect providers capable of building their own AI SoCs.

This is not a lecture just for watching. We guarantee 100% hardware implementation and Bit-True verification.

It goes beyond theory or simple simulations. Experience the thrill of seeing the instructor's KCI-indexed academic research and custom-designed circuits operate flawlessly on actual FPGA hardware. All source code, including the self-developed RISC-V CPU, is transparently disclosed, allowing anyone to freely use, reproduce, and verify it using only an entry-level FPGA (Arty S7-25) and free tools (Vivado).

Seamless Full-stack Roadmap: From Basics to mini LLM Accelerators

Every lecture is not an isolated fragment, but part of a journey toward completing a single, massive system.

Step 1: AI Theory and Image Processing Fundamentals (Including Machine Learning)
Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)
Step 3: RISC-V CPU Design and System Integration
Step 4: Advanced AI SoC Implementation and Expansion to mini LLM Acceleration Platform (Continuous content updates)

Objective Verification Metrics

All design deliverables of this course have undergone rigorous verification against global standards and by the academic community.

RISC-V Architecture Verification: Self-developed RISC-V CPU passed the international foundation's official Architectural Compliance Test (ACT) and source code released (GitHub)
Academic Authority: 4 single-author academic papers (KCI Grade A prestigious indexed journal IJIBC)
Global Recognition: Published two global Amazon technical books (Reached #3 Bestseller)
Actual operation verified: Core IPs such as RV32I CPU, NPU, Vision System, GPS, Transformer, and AURA-Edge SoC are fully operational in the Arty S7 environment.

Take on the challenge. By the time you finish the process of uploading code to the board and verifying the results yourself, you will have leveled up into a hardware engineer with a completely different perspective.

YouTube:@EdgeChipLab
GitHub (Source Code and Projects):github.com/estlit

Curriculum

All

10 lectures ∙ (4hr 39min)

Section 1. Design Fundamentals — Basic Concepts of Computation, Precision, and Verification

1 lectures ∙ (44min)

1. Design Fundamentals — The Language for Reading MNIST NPU Specifications
44:44

Section 2. Python — Building and Training a Reference Model

2 lectures ∙ (52min)

2. Python Golden Model — The Hardware Answer Key
26:47
3. Training — Weight Generation and Integer Quantization
25:52

Section 3. Feature Extraction Circuit — Line Buffer and 4-Channel MAC

1 lectures ∙ (29min)

4. Conv Layer RTL — Line Buffer and 4-Channel Parallel MAC Lecture Video
29:56

Section 4. Transformation and Decision Circuits — From Vectors to Answers

2 lectures ∙ (54min)

Section 5. Integration and Verification — Proving on an FPGA board

2 lectures ∙ (49min)

Section 6. Expansion — Accelerator to Processor

1 lectures ∙ (25min)

Section 7. Setting up the practice environment — Must check before simulation

1 lectures ∙ (21min)

Published: 07/24/2026

Last updated: 07/24/2026

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Building an MNIST NPU with FPGA — From RTL to Bit-True Verification

What you will gain after the course

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HelloThis is EdgeChipLab

Curriculum

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EdgeChipLab's other courses

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Recommended for
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Hello
This is EdgeChipLab