Building an MNIST NPU with FPGA — From RTL to Bit-True Verification

Putting a neural network on an FPGA—the phrase is familiar, but few have actually done it. If you want to stay a step ahead in capstone projects, competitions, or graduation projects, you must be able to go beyond just training a model and actually build and prove how those computations run inside a real chip. This course bridges that exact gap between theory and physical hardware. You will complete a neural network accelerator (NPU) for MNIST digit recognition from start to finish—from reading specifications to Python golden models, Verilog RTL design, and FPGA verification. From Conv layers made with line buffers and parallel MACs, through ReLU, MaxPool, and Flatten, to fully connected layers and Argmax—you will integrate nine blocks into a single chip and prove for yourself that "the Python reference and the hardware output do not differ by even a single bit (Bit-True)." I have even included how to overcome those frustrating moments when the simulation runs fine but the results are subtly different. I will guide you through practical know-how that general deep learning textbooks don't cover, such as integer quantization, array axis reordering, and accumulator overflow prevention. I have distilled the trial and error I experienced over years of RISC-V CPU design and FPGA Bit-True verification into this course so that you don't have to repeat them. By the end of the class, you will have a completed hardware project that allows you to say, "I designed and verified it myself."