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Practical Hardware with FPGA — From Digital Clocks to Real-Time Camera Video

This course is for those who have learned Verilog syntax but are stuck wondering, "So, what should I build?" With just a single FPGA board, you will directly design four types of hardware: a digital clock, an ultrasonic distance sensor, an OLED display, and real-time camera video. The difficulty progresses from output to input/control, display, and finally video, allowing you to master digital design through hands-on experience with visible results. An active professor with 30 years of experience in the semiconductor industry teaches only content that has been verified on actual FPGAs.

1 learners are taking this course

Level Basic

Course period Unlimited

FPGA
FPGA
Verilog HDL
Verilog HDL
vivado
vivado
simulation
simulation
digital-logic
digital-logic
FPGA
FPGA
Verilog HDL
Verilog HDL
vivado
vivado
simulation
simulation
digital-logic
digital-logic

What you will gain after the course

  • The ability to directly create hardware that actually operates (clocks, distance sensors, displays, cameras) using FPGAs.

  • The ability to independently implement core digital design circuits such as counters, frequency dividers, TDM, and FSM.

  • Ability to connect and control Pmod peripherals (7-segment, ultrasonic, OLED, camera) to an FPGA

  • Practical interface design experience in SPI communication, Clock Domain Crossing (CDC), frame buffers, etc.

  • The entire workflow from testbench simulation verification to Vivado hardware implementation.

  • 4 tangible completed projects you can use immediately for your portfolio and interviews

■ This course is

Many people have learned Verilog syntax but get stuck on the question, "So, what do I actually build with this?" This course is the answer. Using a single FPGA board and a few peripherals, you will directly design four pieces of hardware that actually function. The difficulty increases in the following order: Output (Digital Clock) → Input/Control (Ultrasonic Sensor) → Display (OLED) → Real-time Video (Camera). At each stage, you will gain a hands-on understanding of the core concepts of digital design.

■ Four hands-on labs (each with visible results)

· Lab 1. 7-Segment Digital Clock — Complete an MM:SS clock using counters, frequency division, and TDM

· Lab 2. Smart Ultrasonic Measurement System — Distance measurement and LED alarm using ToF principles and FSM

· Lab 3. OLED Image Display — Displaying, switching, and animating images via SPI

· Lab 4. Real-time Camera Image Processing — Real-time output of camera video to OLED via CDC and Frame Buffer

■ Flow of each practice (Common)

Overview/Theory → RTL Code Analysis → Vivado Design Practice → Simulation Verification → FPGA Hardware Operation

You will experience the entire process of actual design, operation, and verification, rather than just knowing the theory.

■ Key Features of This Course

· 4 visible results — clock, sensor, display, and camera. These can be used immediately for portfolios and interviews.

· A complete curriculum where the difficulty level rises naturally, from simple output to real-time video.

· The final Lab 4 synthesizes the previous exercises — it reuses the OLED control from Lab 3 to complete the camera system.

· Full disclosure of all source code (RTL·Testbench·XDC·Python) on GitHub — download and reproduce immediately

■ Recommended for the following people

· Those who have learned Verilog syntax but feel lost on what to actually create

· Undergraduate students majoring in the field who want to create visible results using FPGA

· Those preparing for jobs in the semiconductor or embedded sectors who need a hands-on portfolio

· Those who have only done simulations and are new to actual board and peripheral device control

■ Prerequisites

· Basic Verilog-HDL (If you are lacking in syntax, you can pre-study with free videos)

· Basics of Digital Logic Circuits

· Vivado installation and basic usage

■ Practice Environment

· FPGA Board: Digilent Arty S7-25

· Peripherals: Pmod SSD ×2, Pmod MAXSONAR, Pmod OLEDrgb(SSD1331), OV2640 Camera

(The components required for each lab will be guided within the respective lecture)

· Tool: Xilinx Vivado (Free)

· Practice Source Code: Fully available on GitHub (github.com/estlit/SemiconductorSchool-Labs)

■ Reference

All design and implementation content in this lecture was personally created by the instructor, and the narration (voice) was produced using TTS.

Recommended for
these people

Who is this course right for?

  • Those who have learned Verilog syntax but feel lost about what to actually create.

  • An electronics and computer engineering student who wants to create visible results using FPGA.

  • Those who are preparing for employment in the semiconductor or embedded sectors and need a practical project portfolio.

  • Those who have only done simulations and are new to actual board and peripheral control

Need to know before starting?

  • Verilog-HDL Basics (If you are lacking in grammar, you can pre-study with the free YouTube videos I produced)

  • Basics of Digital Logic Circuits

  • Vivado Installation and Basic Usage

Hello
This is EdgeChipLab

I have 30 years of experience in the semiconductor industry (Samsung Electronics) and am currently a university professor.

I served as a system semiconductor researcher in the Samsung Electronics DS division, Director of the UK and Germany subsidiaries, and Head of the System LSI Marketing and Sales Group; I am currently teaching next-generation semiconductor design at a university.

From transistors to CPU, NPU, and AI SoC, I teach the process of making self-designed circuits operate on actual FPGAs. In particular, these lectures are not a collection of fragmented knowledge from the internet; they are the results of the instructor's own academic research and proven designs implemented on real FPGA hardware and verified as Bit-True. All source code, including the self-developed RISC-V CPU, is released on GitHub, allowing anyone to personally reproduce and verify the results using only an entry-level FPGA (Arty S7-25) and free tools (Vivado).

All lectures are connected through a single curriculum. Starting with AI theory, it progresses to image processing and AI accelerator (NPU) design and verification. It will further expand into advanced and professional courses covering RISC-V CPU, advanced NPU, AI SoC, and mini LLM. (Content is continuously updated.)

[Verifiable History]

- Self-developed RISC-V CPU — Passed the RISC-V International Foundation's official Architectural Compliance Test (ACT), source code released

- 4 single-author academic papers (published in IJIBC, a renowned KCI-indexed journal)

- Two books published on Amazon (Ranked #3 Bestseller, including AI NPU System Design with Python and Verilog)

- Verified operation of RV32I CPU, NPU, Vision, and AURA-Edge SoC on Arty S7

YouTube @EdgeChipLab · GitHub github.com/estlit

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Curriculum

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4 lectures ∙ (2hr 24min)

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