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AI Accelerator with FPGA — From Image Processing to CNN Training and Hardware Verification

Name: AI Accelerator with FPGA — From Image Processing to CNN Training and Hardware Verification
Price: 132000 KRW

Many people have learned FPGA and Verilog but get stuck at the question, "So, how do I actually build an AI accelerator?" This course resolves that curiosity. Using just a single entry-level FPGA and free tools, you will start from a hand-designed 3×3 kernel, train a CNN yourself, quantize the trained weights to INT8 to load onto the hardware, and verify that the results are Bit-True—not deviating by even a single bit from the Python model. As a professor with 30 years of experience in the semiconductor industry, I teach only verified content as 'working circuits' on actual FPGAs. By gaining the experience of designing and proving it yourself rather than just learning theory, you will acquire practical skills that are recognized in the fabless design and AI semiconductor fields.

2 learners are taking this course

Level Intermediate

Course period Unlimited

EdgeChipLab

FPGA

Verilog HDL

vivado

CNN

FPGA

Verilog HDL

vivado

CNN

What you will gain after the course

The ability to directly design an image recognition accelerator, from 3×3 kernels to CNNs, and run it on an FPGA.
Practical ability to quantize trained floating-point weights to INT8 (PTQ/QAT) and deploy them onto hardware.
Bit-True verification capability to compare Python reference models and Verilog RTL on a bit-by-bit basis
Ability to implement real-time image processing pipelines (pixel filters, 3×3 convolutions) on FPGA
The ability to directly design hardware-friendly computational structures such as line buffers, Winner-Take-All, and Argmax.
Practical experience in handling two clock domains and meeting timing requirements in FPGA implementation.
A working AI accelerator result, completed using only free tools and a single FPGA, that can be used in a portfolio.

■ Course Introduction

This is a hands-on course where you will design, train, and verify an AI accelerator (NPU) using only an entry-level FPGA (Arty S7-25) and free tools (Vivado). Starting from a hand-designed 3×3 kernel, you will train a CNN yourself, quantize the trained floating-point weights to INT8 to load onto the FPGA, and verify that the results are "Bit-True"—matching the Python reference model without a single bit of error. Moving beyond mere conceptual explanations, you will see your designed circuits operate on actual hardware, and all source code is publicly available on GitHub.

■ What this course covers

It spans two tracks, from image processing to AI accelerator design.

· Real-time image processing — Pixel streaming pipeline, 3×3 convolution, line buffer

· Intro to AI Acceleration — Fixed Kernel Classifier → CNN Training & Quantization (PTQ·QAT) → Bit-True Verification of Training Weights

It starts with manual design and progresses all the way to verifying machine-learned weights on hardware.

■ Recommended for the following people

· Junior engineers or students preparing for semiconductor fabless front-end design positions who feel lost because they only know the theory and lack hands-on design experience.

· Junior engineers who have experience with FPGA and Verilog but have not yet reached the level of designing and verifying AI accelerators on their own

· Electronics or Computer Engineering students who need a portfolio demonstrating the physical implementation of AI semiconductors

· Those who wish to transition to the AI system semiconductor field and need a way to prove their practical hardware capabilities

■ After taking this course

· The ability to directly design image recognition accelerators, from 3×3 kernels to CNNs, and run them on FPGAs

· Practical ability to quantize learned floating-point weights to INT8 (PTQ·QAT) and deploy them onto hardware

· Bit-True verification skills to compare Python reference models and Verilog RTL bit-by-bit

· The ability to directly design hardware-friendly computational structures such as line buffers, Winner-Take-All, and Argmax.

· A functional AI accelerator output that can be used immediately in portfolios and interviews

■ Prerequisites

· Basic C programming, basic digital logic circuits

· Experience with Verilog-HDL syntax and FPGA synthesis/implementation

· Basic use of Python

· Basic concepts of CNNs and neural networks

■ Preparation before taking the course (Important)

This course assumes that the Vivado and Python environments are installed and that you are able to run basic simulations. The setup of the basic environment below will not be covered in detail during the lecture, so please prepare it in advance.

- Vivado installation and basic usage

- Python (Anaconda/Jupyter) installation

- Basic Verilog-HDL

The basics mentioned above are covered in free videos on my YouTube channel (@EdgeChipLab), or you may refer to other available resources. This course focuses on "image processing and AI accelerator design, training, and verification" based on those fundamentals.

■ Practice Environment · Requirements

· FPGA Board: Digilent Arty S7-25

· Display: Pmod OLEDrgb (SSD1331, 96×64) — For displaying input and result images

· Tools: Xilinx Vivado (Free), Python (Anaconda/Jupyter)

· Practice Source Code: Fully available on GitHub (RTL·Python·Testbench·.mem)

· Input uses stored images (.mem), and no camera is required.

· Learn everything from video processing to Vivado simulation even without a board or OLED

■ Unique strengths of this course

· A complete loop leading from design → training → hardware verification

· 100% Bit-True Verification — proving it's not just 'working,' but 'exactly the same as Python'

· Complete the course anytime, anywhere with a single entry-level FPGA and free tools.

· Fully public on GitHub for immediate download and reproduction

· A current professor with 30 years of experience in the semiconductor industry delivers only content verified on actual FPGAs.

■ Reference

· All design and implementation content in this lecture was created by the instructor, and the narration (voice) was produced using TTS.

Recommended for
these people

Who is this course right for?

Those who are preparing for a job in semiconductor fabless front-end design but feel lost because they only know the theory and have no hands-on design experience.
Junior engineers who have experience with FPGA and Verilog but have not yet reached the level of designing and verifying AI accelerators on their own.
Electronics and Computer Engineering majors who need a portfolio demonstrating the physical implementation of AI semiconductors.
Those who are looking to transition into the AI system semiconductor field and need a way to prove their practical hardware capabilities.

Need to know before starting?

C Language Basics
Basics of Digital Logic Circuits
Verilog-HDL Syntax (Prerequisite learning available through free Level 1 YouTube videos)
Vivado · Python (Anaconda/Jupyter) Installation and Basic Simulation Execution

Hello
This is EdgeChipLab

I have 30 years of experience in the semiconductor industry (Samsung Electronics) and am currently a university professor.

I served as a system semiconductor researcher in the Samsung Electronics DS division, Director of the UK and Germany subsidiaries, and Head of the System LSI Marketing and Sales Group; I am currently teaching next-generation semiconductor design at a university.

From transistors to CPU, NPU, and AI SoC, I teach the process of making self-designed circuits operate on actual FPGAs. In particular, these lectures are not a collection of fragmented knowledge from the internet; they are the results of the instructor's own academic research and proven designs implemented on real FPGA hardware and verified as Bit-True. All source code, including the self-developed RISC-V CPU, is released on GitHub, allowing anyone to personally reproduce and verify the results using only an entry-level FPGA (Arty S7-25) and free tools (Vivado).

All lectures are connected through a single curriculum. Starting with AI theory, it progresses to image processing and AI accelerator (NPU) design and verification. It will further expand into advanced and professional courses covering RISC-V CPU, advanced NPU, AI SoC, and mini LLM. (Content is continuously updated.)

[Verifiable History]

- Self-developed RISC-V CPU — Passed the RISC-V International Foundation's official Architectural Compliance Test (ACT), source code released

- 4 single-author academic papers (published in IJIBC, a renowned KCI-indexed journal)

- Two books published on Amazon (Ranked #3 Bestseller, including AI NPU System Design with Python and Verilog)

- Verified operation of RV32I CPU, NPU, Vision, and AURA-Edge SoC on Arty S7

YouTube @EdgeChipLab · GitHub github.com/estlit

Curriculum

All

5 lectures ∙ (3hr 6min)

Section 1. Real-time image processing

2 lectures ∙ (1hr 5min)

Section 2. Introduction to AI Acceleration: Directional Feature Recognition Line Classifier

3 lectures ∙ (2hr 1min)

3. Fixed Kernel Line Classifier — FPGA that knows the direction without training
37:55
4. CNN Training and Quantization (PTQ·QAT)
44:23
5. Learning Weight FPGA Verification — Bit-True
38:54

Published: 07/22/2026

Last updated: 07/22/2026

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