AI Accelerator with FPGA — From Image Processing to CNN Training and Hardware Verification

Name: AI Accelerator with FPGA — From Image Processing to CNN Training and Hardware Verification
Price: 220000 KRW

Many people have learned FPGA and Verilog but get stuck at the question, "So, how do I actually build an AI accelerator?" This course resolves that curiosity. Using just a single entry-level FPGA and free tools, you will start from a hand-designed 3×3 kernel, train a CNN yourself, quantize the trained weights to INT8 to load onto the hardware, and verify that the results are Bit-True—not deviating by even a single bit from the Python model. As a professor with 30 years of experience in the semiconductor industry, I teach only verified content as 'working circuits' on actual FPGAs. By gaining the experience of designing and proving it yourself rather than just learning theory, you will acquire practical skills that are recognized in the fabless design and AI semiconductor fields.

9 learners are taking this course

Level Intermediate

Course period Unlimited

EdgeChipLab

FPGA

Verilog HDL

vivado

CNN

FPGA

Verilog HDL

vivado

CNN

What you will gain after the course

The ability to directly design an image recognition accelerator, from 3×3 kernels to CNNs, and run it on an FPGA.
Practical ability to quantize trained floating-point weights to INT8 (PTQ/QAT) and deploy them onto hardware.
Bit-True verification capability to compare Python reference models and Verilog RTL on a bit-by-bit basis
Ability to implement real-time image processing pipelines (pixel filters, 3×3 convolutions) on FPGA
The ability to directly design hardware-friendly computational structures such as line buffers, Winner-Take-All, and Argmax.
Practical experience in handling two clock domains and meeting timing requirements in FPGA implementation.
A working AI accelerator result, completed using only free tools and a single FPGA, that can be used in a portfolio.

■ Course Introduction

This is a hands-on course where you will design, train, and verify an AI accelerator (NPU) using only an entry-level FPGA (Arty S7-25) and free tools (Vivado). Starting from a hand-designed 3×3 kernel, you will train a CNN yourself, quantize the trained floating-point weights to INT8 to load onto the FPGA, and verify that the results are "Bit-True"—matching the Python reference model without a single bit of error. Moving beyond mere conceptual explanations, you will see your designed circuits operate on actual hardware, and all source code is publicly available on GitHub.

■ What this course covers

It spans two tracks, from image processing to AI accelerator design.

· Real-time image processing — Pixel streaming pipeline, 3×3 convolution, line buffer

· Intro to AI Acceleration — Fixed Kernel Classifier → CNN Training & Quantization (PTQ·QAT) → Bit-True Verification of Training Weights

It starts with manual design and progresses all the way to verifying machine-learned weights on hardware.

■ Recommended for the following people

· Junior engineers or students preparing for semiconductor fabless front-end design positions who feel lost because they only know the theory and lack hands-on design experience.

· Junior engineers who have experience with FPGA and Verilog but have not yet reached the level of designing and verifying AI accelerators on their own

· Electronics or Computer Engineering students who need a portfolio demonstrating the physical implementation of AI semiconductors

· Those who wish to transition to the AI system semiconductor field and need a way to prove their practical hardware capabilities

■ After taking this course

· The ability to directly design image recognition accelerators, from 3×3 kernels to CNNs, and run them on FPGAs

· Practical ability to quantize learned floating-point weights to INT8 (PTQ·QAT) and deploy them onto hardware

· Bit-True verification skills to compare Python reference models and Verilog RTL bit-by-bit

· The ability to directly design hardware-friendly computational structures such as line buffers, Winner-Take-All, and Argmax.

· A functional AI accelerator output that can be used immediately in portfolios and interviews

■ Prerequisites

· Basic C programming, basic digital logic circuits

· Experience with Verilog-HDL syntax and FPGA synthesis/implementation

· Basic use of Python

· Basic concepts of CNNs and neural networks

■ Preparation before taking the course (Important)

This course assumes that the Vivado and Python environments are installed and that you are able to run basic simulations. The setup of the basic environment below will not be covered in detail during the lecture, so please prepare it in advance.

- Vivado installation and basic usage

- Python (Anaconda/Jupyter) installation

- Basic Verilog-HDL

The basics mentioned above are covered in free videos on my YouTube channel (@EdgeChipLab), or you may refer to other available resources. This course focuses on "image processing and AI accelerator design, training, and verification" based on those fundamentals.

■ Practice Environment · Requirements

· FPGA Board: Digilent Arty S7-25

· Display: Pmod OLEDrgb (SSD1331, 96×64) — For displaying input and result images

· Tools: Xilinx Vivado (Free), Python (Anaconda/Jupyter)

· Practice Source Code: Fully available on GitHub (RTL·Python·Testbench·.mem)

· Input uses stored images (.mem), and no camera is required.

· Learn everything from video processing to Vivado simulation even without a board or OLED

■ Unique strengths of this course

· A complete loop leading from design → training → hardware verification

· 100% Bit-True Verification — proving it's not just 'working,' but 'exactly the same as Python'

· Complete the course anytime, anywhere with a single entry-level FPGA and free tools.

· Fully public on GitHub for immediate download and reproduction

· A current professor with 30 years of experience in the semiconductor industry delivers only content verified on actual FPGAs.

■ Reference

· All design and implementation content in this lecture was created by the instructor, and the narration (voice) was produced using TTS.

Recommended for
these people

Who is this course right for?

Those who are preparing for a job in semiconductor fabless front-end design but feel lost because they only know the theory and have no hands-on design experience.
Junior engineers who have experience with FPGA and Verilog but have not yet reached the level of designing and verifying AI accelerators on their own.
Electronics and Computer Engineering majors who need a portfolio demonstrating the physical implementation of AI semiconductors.
Those who are looking to transition into the AI system semiconductor field and need a way to prove their practical hardware capabilities.

Need to know before starting?

C Language Basics
Basics of Digital Logic Circuits
Verilog-HDL Syntax (Prerequisite learning available through free Level 1 YouTube videos)
Vivado · Python (Anaconda/Jupyter) Installation and Basic Simulation Execution

Hello
This is EdgeChipLab

Career Verified

Design and implement AI semiconductors directly on FPGAs

As a current university professor, I have incorporated 30 years of experience in the system semiconductor industry, along with expertise in AI semiconductor research and education.

This is a hands-on curriculum designed by a professor who teaches semiconductor engineering, based on direct design and FPGA verification experience—from starting as a systems semiconductor researcher in Samsung Electronics’ DS Division, to serving as a Director at the company’s UK and German subsidiaries, and then leading the System LSI marketing and sales group.

This is not simply a course on how to use FPGAs.
It is designed to help you understand AI algorithms → directly design NPUs and CPUs in RTL → implement them on an FPGA → verify them on actual hardware → and ultimately expand to AI SoCs.

AI Algorithm → RTL Design → FPGA Implementation → Bit-True Verification → AI SoC

Beyond theory to real-world AI hardware implementation

It is difficult to develop system-level AI semiconductor design capabilities with only fragmented, scattered knowledge.

Students do not stop at using finished black-box IP. The goal is to gradually develop the system design skills needed to design an AI NPU and RISC-V CPU themselves, integrate memory and peripherals, and ultimately build their own AI SoC.

Starting with the fundamentals of transistors and digital circuits, you will progress through FPGAs, CPUs, and NPUs to hardware for accelerating Transformers and LLMs.

We validate the research results on actual FPGA hardware.

This is not a lecture you simply watch. Rather than stopping at theory or basic simulations, you will run AI semiconductor circuits you designed yourself on an actual FPGA and perform Bit-True verification to confirm that the Python model and RTL results match down to the last bit.

The instructor’s research findings, including four KCI-listed papers on AI semiconductors, FPGAs, and RISC-V, are also connected to the educational content, enabling technologies validated through research to be applied to actual designs and FPGA implementations.

We make the source code needed for hands-on practice publicly available, including our self-developed RISC-V CPU, Python code for image training, and Verilog RTL.

Centered around the affordable Arty S7-25 FPGA board and the free Vivado design tool, this course is designed to enable learners to reproduce the entire process of designing, implementing, and verifying their own work.

It is also compatible with Digilent FPGA boards, including the Zybo Z7. You can use it by modifying the XDC pin mapping (board) and clock division parameters (RTL) to match the board.

The 'MNIST NPU with FPGA' course only requires modifying the XDC pin mapping, while courses using an OLED and Camera require modifying the clock division parameters (RTL).

→The lecture exercises are configured with clock division parameters based on Arty S7’s 100 MHz input clock. Since other boards have different input clocks (for example, Zybo Z7 has 125 MHz), you will need to recalculate the division values so that the target frequency remains the same. If you miss this part, the screen or video may not display properly, which can easily be mistaken for a code error, so please check it.

A Seamless Full-Stack Roadmap: From the Basics to a mini LLM Accelerator

All the lectures are not independent fragments, but a journey toward completing one vast system.

Step 1: AI Theory and Image Processing Fundamentals (including Machine Learning)
Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)
Step 3: RISC-V CPU Design and System Integration
Step 4: Advanced AI SoC Implementation and Expansion into a mini LLM Acceleration Platform (Continuous Content Updates)

Objective verification metrics

All design outcomes from this course have undergone rigorous validation against global standards and by academia.

RISC-V Architecture Verification: In-house developed RISC-V CPU, passed the international foundation’s official compliance test (ACT), with source code released publicly (GitHub)
Academic Authority: Four sole-authored academic papers (published in the prestigious KCI A-rated journal IJIBC)
Global Recognition: Authored and published two global Amazon technology books (reached No. 3 on the bestseller list)
Real-world operation verified: Core IPs including the RV32I CPU, NPU, vision system, GPS, Transformer, and AURA-Edge SoC operate flawlessly in the Arty S7 environment.

Take on the challenge. By the time you complete this process of uploading code directly to the board and verifying the results, you will have leveled up into a hardware engineer with a completely different perspective.

YouTube: @EdgeChipLab
Homepage: www.SemiconductorSchool.co.kr
GitHub (source code and projects):github.com/estlit

Curriculum

All

5 lectures ∙ (3hr 6min)

Section 1. Real-time image processing

2 lectures ∙ (1hr 5min)

Section 2. Introduction to AI Acceleration: Directional Feature Recognition Line Classifier

3 lectures ∙ (2hr 1min)

3. Fixed Kernel Line Classifier — FPGA that knows the direction without training
37:55
4. CNN Training and Quantization (PTQ·QAT)
44:23
5. Learning Weight FPGA Verification — Bit-True
38:54

Published: 07/22/2026

Last updated: 07/22/2026

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[7-Day Complete] Pass MS AI-900 Certification in One Go

jobgreegi

$34.10

Beginner / Machine Learning(ML), Deep Learning(DL), AI, AI Agent

5.0

(17)

Mission

Implementing UART on FPGA

EasyFPGA

$22.00

Basic / FPGA, system-verilog, uart, vivado

5.0

(3)

Mission

UART is the most basic and widely utilized serial communication method, making it a very suitable learning topic for beginners new to FPGA design. In this course, we will thoroughly understand the communication principles and frame structure of UART, and based on this, we will proceed with directly implementing transmit/receive logic through RTL (Register Transfer Level) design. By implementing UART on an FPGA, you can systematically develop your digital circuit design skills and gain experience verifying its operation at the actual hardware level through simulation and verification. Furthermore, by learning the method utilizing the MicroBlaze soft processor and Xilinx UART IP, you will gain a broad understanding of processor-based system design flow and interface configuration. This will enable you to acquire comprehensive development capabilities encompassing both logic design and processor design.

Basic

FPGA, system-verilog, uart

Implementing UART on FPGA

EasyFPGA

$22.00

Basic / FPGA, system-verilog, uart, vivado

5.0

(3)

Mission

Full AI Course 2026: ChatGPT, Gemini, Midjourney, Firefly

Tanmoy Das

$18.70

Beginner / gemini, AI, ChatGPT, Midjourney, Microsoft Copilot

5.0

(1)

Hi Guys. Welcome to my Full AI Course 2026: ChatGPT, Google Gemini, Midjourney, Firefly. In my course you will learn everything about all AI Tools. I have created video lessons on every feature of these AI tools. You will get to see the real practical implementation of how to use every feature of this tools.

Beginner

gemini, AI, ChatGPT

Full AI Course 2026: ChatGPT, Gemini, Midjourney, Firefly

Tanmoy Das

$18.70

Beginner / gemini, AI, ChatGPT, Midjourney, Microsoft Copilot

5.0

(1)

TSMC, the Architect of Overwhelming Advantage: World's No.1 Strategy Know-how

365ENM

$84.70

Beginner / AI, Management, Economics, Computer Architecture

Beyond the technical field of semiconductors, this book provides a multidimensional view of how a single company moves the world. Going beyond simple technical explanations, it analyzes why the United States, China, and Taiwan are clashing over semiconductors, and examines through real cases how TSMC created an overwhelming gap that dominates the market. Centered on founder Morris Chang's leadership and TSMC's success strategies, it offers an opportunity to understand technology and management in an integrated way.

Beginner

AI, Management, Economics

TSMC, the Architect of Overwhelming Advantage: World's No.1 Strategy Know-how

365ENM

$84.70

Beginner / AI, Management, Economics, Computer Architecture

[AI Fundamentals] Understanding CNNs for AI Research Engineers

whitebox

Free

Beginner / Computer Vision(CV), Python, PyTorch, CNN

4.9

(66)

800+

Still lost on CNN even after studying it? I'll concisely explain CNN's core mechanics.

Beginner

Computer Vision(CV), Python, PyTorch

[AI Fundamentals] Understanding CNNs for AI Research Engineers

whitebox

Free

Beginner / Computer Vision(CV), Python, PyTorch, CNN

4.9

(66)

800+

A Complete Dissection of Robotic Systems by an Industry Professional: From Components to Communication

jelly

$15.40

Beginner / Embedded, MCU, ros, robotics, robot, AI, systems

5.0

(2)

Update

Complete Understanding of Robotics High- and Low-Level Controllers, Sensors, and Ultra-High-Speed Communication Concepts Through the Unitree Go2 Example

Beginner

Embedded, MCU, ros

A Complete Dissection of Robotic Systems by an Industry Professional: From Components to Communication

jelly

$15.40

Beginner / Embedded, MCU, ros, robotics, robot, AI, systems

5.0

(2)

Update

AI Accelerator with FPGA — From Image Processing to CNN Training and Hardware Verification

What you will gain after the course

Recommended for these people

HelloThis is EdgeChipLab

Design and implement AI semiconductors directly on FPGAs

Beyond theory to real-world AI hardware implementation

We validate the research results on actual FPGA hardware.

A Seamless Full-Stack Roadmap: From the Basics to a mini LLM Accelerator

Objective verification metrics

Curriculum

Reviews

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Hello
This is EdgeChipLab