Directly design and implement AI semiconductors using FPGA
As a current university professor, I have incorporated 30 years of experience in the system semiconductor industry along with AI semiconductor research and education know-how.
This is a practical curriculum directly designed and verified on FPGA by a professor who currently teaches semiconductor engineering, following a career that began as a system semiconductor researcher at Samsung Electronics DS Division and included roles as Director of the UK and German subsidiaries, as well as Head of the System LSI Marketing and Sales Group.
This is not just a course for learning how to use FPGAs.
It aims for a process of understanding AI algorithms → designing NPUs and CPUs directly with RTL → implementing them on FPGAs → verifying them on actual hardware → and ultimately expanding to AI SoCs..
AI Algorithm → RTL Design → FPGA Implementation → Bit-True Verification → AI SoC
Beyond theory, toward actual AI hardware implementation
It is difficult to reach a system-level AI semiconductor design capability with only scattered, fragmentary knowledge.
Students will not stop at simply using pre-made black-box IPs. The goal is to step-by-step build system design capabilities to directly design AI NPUs and RISC-V CPUs, integrate memory and peripherals, and ultimately construct their own AI SoC.
Starting from the basics of transistors and digital circuits, it connects through FPGA, CPU, and NPU all the way to Transformer and LLM acceleration hardware.
Verify research results with actual FPGA hardware.
This is not a lecture just for watching. We don't stop at theory or simple simulations; you will operate the AI semiconductor circuits you designed yourself on an actual FPGA and perform Bit-True verification, ensuring the Python model and RTL results match down to a single bit.
The instructor's research results, including four KCI-indexed papers related to AI semiconductors, FPGAs, and RISC-V, are also linked to the educational content, bridging research-proven technologies to actual design and FPGA implementation.
We are releasing the source code necessary for practice, including our self-developed RISC-V CPU, Python code for image training, and Verilog RTL.
It is structured around the entry-level Arty S7-25 FPGA board and the free Vivado design tool, allowing learners to reproduce the entire process of designing, implementing, and verifying for themselves.
Seamless Full-Stack Roadmap: From Basics to mini LLM Accelerator
Every lecture is not just an isolated fragment, but a journey toward completing one massive system.
Step 1: AI Theory and Image Processing Basics (Including Machine Learning)
Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)
Step 3: RISC-V CPU Design and System Integration
Step 4: Advanced AI SoC Implementation and Expansion to mini LLM Acceleration Platform (Continuous Content Updates)
Objective Verification Metrics
All design outcomes of this course have undergone rigorous verification by global standards and academia.
RISC-V Architecture Verification: Self-developed RISC-V CPU, passed the official International Foundation Compliance Test (ACT), and source code released (GitHub)
Academic Authority: 4 papers as a sole author (IJIBC, a KCI Grade A-rated prestigious academic journal)
Global Recognition: Published 2 global Amazon technical books (Reached #3 Bestseller)
Actual operation verification completed: Core IPs including RV32I CPU, NPU, vision systems, GPS, Transformer, and AURA-Edge SoC operate perfectly in the Arty S7 environment
Take the challenge. By the time you finish this process of uploading code to the board yourself and verifying the results, you will have leveled up into a hardware engineer with a completely different perspective than before.