Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)

Name: Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)
Price: 110000 KRW

This lecture implements a DDR Memory Arbiter.

5 learners are taking this course

Level Basic

Course period Unlimited

alex

Verilog HDL

FPGA

Verilog HDL

FPGA

What you will gain after the course

DDR Arbiter
Image Frame Buffer

This lecture covers implementing the arbiter, the final stage of a DDR memory controller. When using DDR as a frame buffer for image data, DDR access (read/write) can overlap. This typically occurs when the input and output frame rates differ. In such cases, you need to design an arbiter to control access (read/write) timing. You must ensure that read and write requests are processed sequentially.

This lecture will implement a DDR arbiter to ensure sequential DDR access without overlapping when the input and output image frame rates differ. The results will be downloaded to the board and verified to be operational.

The structure of the text is as follows.

Chapter 2 describes the HIL-A35T board used in the lab.

Chapter 3 describes the general system configuration.

Chapter 4 implements the program module by module.

Chapter 5 implements the Top Module and verifies the results through simulation.

Chapter 6 generates a bitstream and checks the results on the board.

💾 Please check before taking the class!

This lecture is a text lecture in PDF format and does not provide separate videos.
We provide the source code for the mods described in the lecture.
We will conduct hands-on training on the HIL-A35T development board sold by our company.

Introducing the Knowledge Sharer ✒

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming. I hope my extensive experience will be helpful to you in your learning.

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Who is this course right for?

Verilog aspirants?
Want to learn FPGA?
Anyone who wants to learn ddr Arbiter

Need to know before starting?

verilog
vivado
xilinx fpga

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I have worked as a developer at both large corporations and SMEs for the past 20 years,

I am currently the CEO of a small company.

Key career highlights include

FPGA design using Verilog HDL
- ISP ASIC development for CCTV (approx. 10 years)
- OLED Display inspection equipment development (approx. 3 years)
- Equipment development using FPGA
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Development
- Visual Studio MFC, C++

Curriculum

All

104 lectures

Course Materials:

Lecture resources

Section 1. Overview

4 lectures

Section 2. Hardware Configuration

6 lectures

5. HW Configuration - 0
6. HW Configuration - 1
7. HW Configuration - 2
8. HW Configuration - 3
9. HW Setup - 4
10. HW Configuration - 5

Section 3. System Configuration

2 lectures

Section 4. Program Implementation

69 lectures

Section 5. Top Module Implementation

13 lectures

Section 6. Bitstream generation and result confirmation

8 lectures

Section 7. Etc.

2 lectures

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What you will gain after the course

Introducing the Knowledge Sharer ✒

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