Design and implement AI semiconductors directly on FPGAs
As a current university professor, I have incorporated 30 years of experience in the system semiconductor industry, along with expertise in AI semiconductor research and education.
This is a hands-on curriculum designed by a professor who teaches semiconductor engineering, based on direct design and FPGA verification experience—from starting as a systems semiconductor researcher in Samsung Electronics’ DS Division, to serving as a Director at the company’s UK and German subsidiaries, and then leading the System LSI marketing and sales group.
This is not simply a course on how to use FPGAs.
It is designed to help you understand AI algorithms → directly design NPUs and CPUs in RTL → implement them on an FPGA → verify them on actual hardware → and ultimately expand to AI SoCs.
AI Algorithm → RTL Design → FPGA Implementation → Bit-True Verification → AI SoC
Beyond theory to real-world AI hardware implementation
It is difficult to develop system-level AI semiconductor design capabilities with only fragmented, scattered knowledge.
Students do not stop at using finished black-box IP. The goal is to gradually develop the system design skills needed to design an AI NPU and RISC-V CPU themselves, integrate memory and peripherals, and ultimately build their own AI SoC.
Starting with the fundamentals of transistors and digital circuits, you will progress through FPGAs, CPUs, and NPUs to hardware for accelerating Transformers and LLMs.
We validate the research results on actual FPGA hardware.
This is not a lecture you simply watch. Rather than stopping at theory or basic simulations, you will run AI semiconductor circuits you designed yourself on an actual FPGA and perform Bit-True verification to confirm that the Python model and RTL results match down to the last bit.
The instructor’s research findings, including four KCI-listed papers on AI semiconductors, FPGAs, and RISC-V, are also connected to the educational content, enabling technologies validated through research to be applied to actual designs and FPGA implementations.
We make the source code needed for hands-on practice publicly available, including our self-developed RISC-V CPU, Python code for image training, and Verilog RTL.
Centered around the affordable Arty S7-25 FPGA board and the free Vivado design tool, this course is designed to enable learners to reproduce the entire process of designing, implementing, and verifying their own work.
It is also compatible with Digilent FPGA boards, including the Zybo Z7. You can use it by modifying the XDC pin mapping (board) and clock division parameters (RTL) to match the board.
The 'MNIST NPU with FPGA' course only requires modifying the XDC pin mapping, while courses using an OLED and Camera require modifying the clock division parameters (RTL).
→The lecture exercises are configured with clock division parameters based on Arty S7’s 100 MHz input clock. Since other boards have different input clocks (for example, Zybo Z7 has 125 MHz), you will need to recalculate the division values so that the target frequency remains the same. If you miss this part, the screen or video may not display properly, which can easily be mistaken for a code error, so please check it.
A Seamless Full-Stack Roadmap: From the Basics to a mini LLM Accelerator
All the lectures are not independent fragments, but a journey toward completing one vast system.
Step 1: AI Theory and Image Processing Fundamentals (including Machine Learning)
Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)
Step 3: RISC-V CPU Design and System Integration
Step 4: Advanced AI SoC Implementation and Expansion into a mini LLM Acceleration Platform (Continuous Content Updates)
Objective verification metrics
All design outcomes from this course have undergone rigorous validation against global standards and by academia.
RISC-V Architecture Verification: In-house developed RISC-V CPU, passed the international foundation’s official compliance test (ACT), with source code released publicly (GitHub)
Academic Authority: Four sole-authored academic papers (published in the prestigious KCI A-rated journal IJIBC)
Global Recognition: Authored and published two global Amazon technology books (reached No. 3 on the bestseller list)
Real-world operation verified: Core IPs including the RV32I CPU, NPU, vision system, GPS, Transformer, and AURA-Edge SoC operate flawlessly in the Arty S7 environment.
Take on the challenge. By the time you complete this process of uploading code directly to the board and verifying the results, you will have leveled up into a hardware engineer with a completely different perspective.
