RISC-V CPU Design for FPGA Implementation ① Learning RV32I Instruction Structure and Execution Principles with Python

When people decide to build a CPU, they usually start by looking for a circuit diagram. However, the moment they unfold the schematic, unanswerable questions arise: Why must this block be here? Why are there two ports for reading registers? The answers all lie within the instructions. Once you know what an instruction requires, the necessary circuitry is determined. It doesn't work the other way around. There are already many RISC-V lectures available. However, most of them simply display values on a slide, say "This is how it works," and move on. Students have no way to verify if those values are correct. This course provides a Python-based instruction execution simulator. When you type `run ADD`, the machine code is assembled on the spot, the 32 bits are laid out by field, and you can see exactly how the registers change on your screen. Every number in the textbook is a result of this tool's execution, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators often have installation barriers. This tool only requires Python. You don't need a board, a license, or a complex setup. This is a process of executing all 40 RV32I instructions without skipping a single one, discovering for yourself what the circuit needs to do.

2 learners are taking this course

Level Basic

Course period Unlimited

riscv
riscv
cpu-architecture
cpu-architecture
instruction-set-architecture
instruction-set-architecture
FPGA
FPGA
Computer Architecture
Computer Architecture
riscv
riscv
cpu-architecture
cpu-architecture
instruction-set-architecture
instruction-set-architecture
FPGA
FPGA
Computer Architecture
Computer Architecture

What you will gain after the course

  • · You will acquire the instruction set design criteria for designing your own CPU.

  • · You can flesh out CPU design topics for Capstone Design, competition entries, and graduation projects.

  • · You can identify the format of a 32-bit machine code, parse the fields, and read what instruction it is.

  • · You can directly execute 40 RV32I instructions and check the changes in registers and memory.

  • · You can explain which circuit blocks a single instruction passes through and how the 13 control signals are determined.

  • · You will have a Python command execution simulator that can be rerun at any time.

  • · You can understand the meaning of Bit-True verification and determine what it guarantees when someone says they have "verified" it.

  • · In technical interviews, you will be able to answer questions about CPU operating principles based on your experience of actually running them, rather than just reciting memorized sentences.

Build your own CPU on an FPGA.

The CPU is the brain of the computer. However, there aren't many lectures that systematically teach you how to design a CPU yourself. Most start by showing RTL code or explaining the datapath. But the real question is this.

Why must a CPU have this specific structure?

Why are there 32 registers?

Why is an ALU necessary?

Why are there two read ports?

Why does Write Back exist?

The answers to all these questions lie within the instructions. A CPU is a circuit created to execute instructions. If you do not understand the instructions, you cannot understand the CPU. This course is a process of learning instructions from the perspective of someone who builds a CPU.


Goals of this course

The goal of this lecture is not to memorize RV32I instructions. It is to build the foundation for designing your own RISC-V CPU that operates on an FPGA. Moving forward, you will

· Single-Cycle CPU

· Pipeline CPU

· You will proceed all the way to FPGA implementation.

This process is the very first step.


■ Why this order?

Many people study RTL first to build a CPU. However, the order is the opposite.

Instruction→Required Action→Datapath→Control Signal→RTL→FPGA

A CPU is the result of implementing the functions required by instructions. Let's take ADD as an example.

Two registers must be read, the ALU must perform the calculation, and the result must be written back to a register. These requirements determine the register file, ALU, MUX, and control unit.

This is also why there are two read ports. It is because none of the 40 RV32I instructions read more than two registers. Once you understand the instructions, you can see why that specific circuit is necessary.


■ What will you learn?

You will directly execute all 40 RV32I instructions. It doesn't just show you add x5, x1, x2 → 0x002082B3. You will personally create machine code, decode it back, execute it, watch the registers change, verify memory transitions, and even trace the datapath and control signals.

Follow a single instruction all the way through to see how it moves within the CPU.


■ Key Features of This Course

This course includes the RV32I Instruction Studio, a Python-based instruction simulator developed by the instructor. You don't need a separate FPGA board. You don't even need complex simulators.

As long as Python is installed

· Instruction execution

· Machine code generation

· Decoding

· Register check

· Memory check

· Check Datapath

· Control signal verification can all be performed directly.


All numbers in the textbook are generated by this tool, and you can reproduce the same results.

· Executes all 40 instructions — these are not examples selected only from frequently used ones

· Training begins only after 1,231 self-verification tests pass

· We intentionally plant 14 defects to test whether the verification process actually catches them.

· No external libraries — total 550KB, starts with a single line after extraction.


■ Curriculum

Section 1. Understanding the Basics of CPU

1. How the CPU executes instructions — Practice environment and registers

2. 32-bit Instruction Structure and Immediate Values

Section 2. Execution of RV32I Instructions

3. Arithmetic, Logical, and Shift Instructions

4. Load/Store · Branch · JAL/JALR Instructions

Section 3. How does the CPU work?

5. Single-Cycle Datapath and Control Signals

Section 4. CPU Verification and Wrap-up

6. Bit-True Verification and Next Step Roadmap

Each lesson is followed by a Lab. It consists of execution order, screen confirmation, self-check items, and example solutions.

It is organized into four steps, so it shows exactly what to input and in what order.


■ Recommended for the following people

· Those who want to implement a CPU directly on an FPGA

· Those who are starting CPU design for the first time

· Those who want to learn RISC-V systematically

· Those who want to bridge the gap between computer architecture and RTL design

· Those who want to implement a CPU for capstone designs or competitions

· Those preparing for employment in the system semiconductor and fabless sectors


■ Practice Environment

All you need are Python and Jupyter Notebook.

https://github.com/estlit/SemiconductorSchool-Labs

→ Level4_Lab_RV32I_Instruction_Studio.zip

Unzip the file, and you can get started with just the one line below in Jupyter.

%run Lab01.py


■ Upon completing the lecture

You will

· Understand RV32I instructions and

· Can explain the CPU datapath and

· Understand why control signals are necessary

· You will establish the foundation for implementing a CPU on an FPGA

And in the next course, you will implement the instructions learned this time using Verilog RTL and actually run them on an FPGA board.

Volume 1 RV32I Instruction Structure and Execution ← You are here

Volume 2 TinyRV32I · 5-Stage Pipeline and FPGA Implementation

Volume 3 Standard CPU · 40 Instructions and Hazard Control

Volume 4 Vision·NPU SoC · Camera and Accelerator Integration

This is the first step in the long journey of building a CPU.

Start now.

Recommended for
these people

Who is this course right for?

  • · Those who want to design their own CPU directly in hardware

  • · System software and firmware developers who want to learn the RISC-V architecture through hands-on practice

  • · Those who want to understand Instruction Set Architecture (ISA) through execution rather than just specification documents

  • · Undergraduate and graduate students preparing for FPGA-based processor design

  • · Those who need CPU architecture skills while preparing for employment in the system semiconductor and fabless fields

  • · Those who need to interpret assembly and register states in practical embedded development.

  • · Those who want to check CPU operation in a practice environment without a commercial debugger license

Need to know before starting?

  • Python basics (being able to run code and read the results is sufficient)

  • Computer Architecture Basics (You can follow along even without this knowledge)

Hello
This is EdgeChipLab

Career Verified

As a current university professor, I have incorporated 30 years of system semiconductor expertise.

This is a practical curriculum directly designed and verified by a professor of semiconductor engineering, whose career spans from a system semiconductor researcher at Samsung Electronics' DS Division to Director of UK and German subsidiaries and Head of the System LSI Marketing & Sales Group.

 

Level up your engineering capabilities by going beyond theory to actual hardware implementation.

There are realms that scattered, fragmentary knowledge alone can never reach. Students will not merely be users of pre-built black-box IPs; they will design NPUs and CPUs, integrate peripherals, and ultimately evolve into system architect providers capable of building their own AI SoCs.

 

This is not a lecture just for watching. We guarantee 100% hardware implementation and Bit-True verification.

It goes beyond theory or simple simulations. Experience the thrill of seeing the instructor's KCI-indexed academic research and custom-designed circuits operate flawlessly on actual FPGA hardware. All source code, including the self-developed RISC-V CPU, is transparently disclosed, allowing anyone to freely use, reproduce, and verify it using only an entry-level FPGA (Arty S7-25) and free tools (Vivado).

 

Seamless Full-stack Roadmap: From Basics to mini LLM Accelerators

Every lecture is not an isolated fragment, but part of a journey toward completing a single, massive system.

  • Step 1: AI Theory and Image Processing Fundamentals (Including Machine Learning)

  • Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)

  • Step 3: RISC-V CPU Design and System Integration

  • Step 4: Advanced AI SoC Implementation and Expansion to mini LLM Acceleration Platform (Continuous content updates)

     

 

Objective Verification Metrics

All design deliverables of this course have undergone rigorous verification against global standards and by the academic community.

  • RISC-V Architecture Verification: Self-developed RISC-V CPU passed the international foundation's official Architectural Compliance Test (ACT) and source code released (GitHub)

  • Academic Authority: 4 single-author academic papers (KCI Grade A prestigious indexed journal IJIBC)

  • Global Recognition: Published two global Amazon technical books (Reached #3 Bestseller)

  • Actual operation verified: Core IPs such as RV32I CPU, NPU, Vision System, GPS, Transformer, and AURA-Edge SoC are fully operational in the Arty S7 environment.

Take on the challenge. By the time you finish the process of uploading code to the board and verifying the results yourself, you will have leveled up into a hardware engineer with a completely different perspective.

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Curriculum

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6 lectures ∙ (1hr 41min)

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