Verilog FPGA Program 6 - DDR Arbiter (Arty A7-35T)

Name: Verilog FPGA Program 6 - DDR Arbiter (Arty A7-35T)
Price: 110000 KRW
Rating: 5 (1 reviews)

This lecture implements DDR Memory Arbiter.

(5.0) 1 reviews

11 learners

Level Basic

Course period Unlimited

alex

FPGA

Verilog HDL

FPGA

Verilog HDL

What you will gain after the course

DDR Arbiter
Image Frame Buffer

This lecture covers implementing the arbiter, the final stage of a DDR memory controller. When using DDR as a frame buffer for image data, DDR access (read/write) can overlap. This typically occurs when the input and output frame rates differ. In such cases, you need to design an arbiter to control access (read/write) timing. You must ensure that read and write requests are processed sequentially.

This lecture will implement a DDR arbiter to ensure sequential DDR access without overlapping when the input and output image frame rates differ. The results will be downloaded to the board and verified to be operational.

The structure of the text is as follows.

Chapter 2 describes the Arty A7-35T board used in the lab.

Chapter 3 describes the general system configuration.

Chapter 4 implements the program module by module.

Chapter 5 implements the Top Module and verifies the results through simulation.

Chapter 6 generates a bitstream and checks the results on the board.

💾 Please check before taking the class!

This lecture is a text lecture in PDF format and does not provide separate videos.
We provide the source code for the mods described in the lecture.
We will be conducting our hands-on training on the Arty A7 development board sold by Digilent.

Introducing the Knowledge Sharer ✒

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming. I hope my extensive experience will be helpful to you in your learning.

Recommended for
these people

Who is this course right for?

Anyone who wants to learn Verilog
Those who wish to learn FPGA
Want to learn ddr Arbiter?

Need to know before starting?

verilog
Vivado
xilinx fpga

Hello
This is alex

1,725

Learners

Reviews

130

Answers

4.8

Rating

Courses

I have worked as a developer at both large corporations and SMEs for the past 20 years,

I am currently the CEO of a small company.

Key career highlights include

FPGA design using Verilog HDL
- ISP ASIC development for CCTV (approx. 10 years)
- OLED Display inspection equipment development (approx. 3 years)
- Equipment development using FPGA
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Development
- Visual Studio MFC, C++

Curriculum

All

103 lectures

Course Materials:

Lecture resources

Section 1. Overview

4 lectures

Section 2. Hardware Configuration

4 lectures

5. HW Config - 0
6. HW Configuration - 6
7. HW Configuration - 7
8. HW Configuration - 8

Section 3. System Configuration

3 lectures

Section 4. Program Implementation

69 lectures

Section 5. Top Module Implementation

13 lectures

Section 6. Bitstream Generation and Result Verification

8 lectures

Section 7. Other

2 lectures

Published: 06/03/2025

Last updated: 06/15/2025

Reviews

All

1 reviews

5.0

1 reviews

neulha
Reviews 15
∙
Average Rating 5.0
06/04/2025
5
31% enrolled

alex's other courses

Check out other courses by the instructor!

STM32 FreeRTOS Implementation

alex

$8.80

Basic / FreeRTOS

4.5

(15)

200+

We will explain in detail how to implement FreeRTOS on STM32 MCU.

Basic

FreeRTOS

STM32 FreeRTOS Implementation

alex

$8.80

Basic / FreeRTOS

4.5

(15)

200+

Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

This lecture implements a DDR Memory Arbiter.

Basic

Verilog HDL, FPGA

Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T)

alex

$63.80

Intermediate / verilog, FPGA

5.0

(5)

Implement LVDS (Serdes) in FPGA.

Intermediate

verilog, FPGA

Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T)

alex

$63.80

Intermediate / verilog, FPGA

5.0

(5)

Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

alex

$84.70

Intermediate / Verilog HDL, FPGA

4.0

(3)

Through this lecture, you will be able to implement a DDR Controller using FPGA.

Intermediate

Verilog HDL, FPGA

Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

alex

$84.70

Intermediate / Verilog HDL, FPGA

4.0

(3)

Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)

alex

$84.70

Basic / FPGA, MicroBlaze, Verilog HDL

Learn how to implement MicroBlaze on Xilinx FPGA.

Basic

FPGA, MicroBlaze, Verilog HDL

Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)

alex

$84.70

Basic / FPGA, MicroBlaze, Verilog HDL

Verilog FPGA Program 1 (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

This is a lecture on designing FPGA programs using Verilog HDL.

Basic

Verilog HDL, FPGA

Verilog FPGA Program 1 (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

Verilog ZYNQ Program 1 (Zynq mini 7020)

alex

$68.20

Intermediate / Verilog HDL, zynq, FPGA, vivado

5.0

(4)

This lecture is about using the Xilinx ZYNQ board. If you understand the contents of this lecture, you will learn the skills to understand Embedded_SW + User_Logic and apply them to practice.

Intermediate

Verilog HDL, zynq, FPGA

Verilog ZYNQ Program 1 (Zynq mini 7020)

alex

$68.20

Intermediate / Verilog HDL, zynq, FPGA, vivado

5.0

(4)

Verilog FPGA Program 1 (Zynq mini 7020)

alex

$84.70

Basic / Verilog HDL, FPGA, zynq

5.0

(4)

In this course, students will learn how to implement Verilog using the Zynq board.

Basic

Verilog HDL, FPGA, zynq

Verilog FPGA Program 1 (Zynq mini 7020)

alex

$84.70

Basic / Verilog HDL, FPGA, zynq

5.0

(4)

Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)

alex

$63.80

Intermediate / FPGA, MicroBlaze

5.0

(3)

This course is an advanced course in Microblaze. Through this course, you will learn how to apply Microblaze.

Intermediate

FPGA, MicroBlaze

Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)

alex

$63.80

Intermediate / FPGA, MicroBlaze

5.0

(3)

Basics of FPGA Utilization Using Verilog

alex

$17.60

Basic / verilog, FPGA

5.0

(10)

100+

Through this course, students will acquire the basic, core knowledge necessary to learn Verilog.

Basic

verilog, FPGA

Basics of FPGA Utilization Using Verilog

alex

$17.60

Basic / verilog, FPGA

5.0

(10)

100+

Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

alex

$84.70

Intermediate / verilog, FPGA

5.0

(7)

100+

Through this lecture, you will be able to implement a DDR controller using FPGA.

Intermediate

verilog, FPGA

Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

alex

$84.70

Intermediate / verilog, FPGA

5.0

(7)

100+

STM32 PWM Implementation

alex

$17.60

Basic / stm32, MCU, pwm

5.0

(2)

This tutorial explains how to implement PWM using STM32 MCU.

Basic

stm32, MCU, pwm

STM32 PWM Implementation

alex

$17.60

Basic / stm32, MCU, pwm

5.0

(2)

STM32 CAN Communication

alex

$17.60

Basic / CAN, MCU

4.4

(7)

100+

This is a text-based lecture explaining how to implement CAN communication using STM32 MCU. Become a master of CAN communication implementation.

Basic

CAN, MCU

STM32 CAN Communication

alex

$17.60

Basic / CAN, MCU

4.4

(7)

100+

STM32 FFT Implementation

alex

$17.60

Intermediate / FFT

5.0

(5)

100+

Implement FFT using DSP Library in STM32.

Intermediate

FFT

STM32 FFT Implementation

alex

$17.60

Intermediate / FFT

5.0

(5)

100+

Verilog FPGA Program 2 (MicroBlaze, Arty A7-35T)

alex

$63.80

Basic / FPGA, MicroBlaze, Verilog HDL

5.0

(5)

100+

This is about implementing MicroBlaze in Xilinx FPGA.

Basic

FPGA, MicroBlaze, Verilog HDL

Verilog FPGA Program 2 (MicroBlaze, Arty A7-35T)

alex

$63.80

Basic / FPGA, MicroBlaze, Verilog HDL

5.0

(5)

100+

Verilog FPGA Program 1 (Arty A7-35T)

alex

$84.70

Basic / Verilog HDL, FPGA

5.0

(16)

100+

FPGA implementation using Verilog

Basic

Verilog HDL, FPGA

Verilog FPGA Program 1 (Arty A7-35T)

alex

$84.70

Basic / Verilog HDL, FPGA

5.0

(16)

100+

Similar courses

Explore other courses in the same field!

Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

This lecture implements a DDR Memory Arbiter.

Basic

Verilog HDL, FPGA

Verilog FPGA Program 6 - DDR Arbiter (HIL-A35T)

alex

$84.70

Basic / Verilog HDL, FPGA

Verilog FPGA Program 1 (Arty A7-35T)

alex

$84.70

Basic / Verilog HDL, FPGA

5.0

(16)

100+

FPGA implementation using Verilog

Basic

Verilog HDL, FPGA

Verilog FPGA Program 1 (Arty A7-35T)

alex

$84.70

Basic / Verilog HDL, FPGA

5.0

(16)

100+

Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

alex

$84.70

Intermediate / verilog, FPGA

5.0

(7)

100+

Through this lecture, you will be able to implement a DDR controller using FPGA.

Intermediate

verilog, FPGA

Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

alex

$84.70

Intermediate / verilog, FPGA

5.0

(7)

100+

Verilog FPGA Program 1 (Zynq mini 7020)

alex

$84.70

Basic / Verilog HDL, FPGA, zynq

5.0

(4)

In this course, students will learn how to implement Verilog using the Zynq board.

Basic

Verilog HDL, FPGA, zynq

Verilog FPGA Program 1 (Zynq mini 7020)

alex

$84.70

Basic / Verilog HDL, FPGA, zynq

5.0

(4)

Implementing UART on FPGA

EasyFPGA

$22.00

Basic / FPGA, system-verilog, uart, vivado

5.0

(3)

Mission

UART is the most basic and widely utilized serial communication method, making it a very suitable learning topic for beginners new to FPGA design. In this course, we will thoroughly understand the communication principles and frame structure of UART, and based on this, we will proceed with directly implementing transmit/receive logic through RTL (Register Transfer Level) design. By implementing UART on an FPGA, you can systematically develop your digital circuit design skills and gain experience verifying its operation at the actual hardware level through simulation and verification. Furthermore, by learning the method utilizing the MicroBlaze soft processor and Xilinx UART IP, you will gain a broad understanding of processor-based system design flow and interface configuration. This will enable you to acquire comprehensive development capabilities encompassing both logic design and processor design.

Basic

FPGA, system-verilog, uart

Implementing UART on FPGA

EasyFPGA

$22.00

Basic / FPGA, system-verilog, uart, vivado

5.0

(3)

Mission

Verilog FPGA Program 6 - DDR Arbiter (Arty A7-35T)

What you will gain after the course

Introducing the Knowledge Sharer ✒

Recommended for these people

HelloThis is alex

Curriculum

Reviews

alex's other courses

Similar courses

Recommended for
these people

Hello
This is alex