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Verilog FPGA Program 6 (ddr Arbiter)

This lecture implements a DDR Memory Arbiter.

(5.0) 3 reviews

12 learners

Level Basic

Course period Unlimited

Verilog HDL
Verilog HDL
FPGA
FPGA
Verilog HDL
Verilog HDL
FPGA
FPGA

What you will gain after the course

  • DDR Arbiter

  • Image Frame Buffer

This lecture covers the implementation of the Arbiter, which is the final stage of the DDR Memory Controller. When using DDR as a frame buffer for image data, there are cases where DDR access (read/write) overlaps. This mainly occurs when the input and output frame rates are different. In such cases, an Arbiter must be designed to adjust the access (read/write) timing. It must ensure that read and write requests are processed sequentially.

In this lecture, we will implement a DDR Arbiter to ensure that DDR access occurs sequentially without overlapping when the frame rates of the input and output images differ. We will then download the results to the board and verify that it operates correctly.

The structure of this document is as follows.

Chapter 2 explains the Arty A7-35T board used in the practice.

Chapter 3 explains the overall system configuration.

Chapter 4 implements the program for each module.

Chapter 5 implements the Top Module and verifies the results through simulation.

Chapter 6 generates the Bitstream and verifies the results on the board.

💾 Please check before taking the course!

  • This course is a text-based lecture in PDF format and does not provide separate videos.

  • We provide all the source code described in the lecture.

  • This course conducts hands-on practice using the Arty A7 board sold by Digilent and the HIL-A35T board sold by our company.

  • The HIL-A35T board can be purchased at our official Smart Store (Smart Store link: https://smartstore.naver.com/ihil)


  • Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachment'.


Instructor Introduction ✒

I have worked as a developer in large corporations and SMEs for over 20 years and currently run a small business. I have developed ISP (Image Signal Processing) ASICs for CCTV and numerous products using FPGAs, such as OLED inspection equipment and DAQ (Data Acquisition Systems). In addition to FPGA, I have extensive experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming. Based on the wide range of experience I have accumulated, I hope to be of help to your learning.

Recommended for
these people

Who is this course right for?

  • Those who want to learn Verilog

  • Those who want to learn FPGA

  • Anyone who wants to learn ddr Arbiter

Need to know before starting?

  • verilog

  • vivado

  • xilinx fpga

Hello
This is alex

Career Verified

1,791

Learners

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Reviews

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Answers

4.8

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Courses

I have worked as a developer at both large corporations and SMEs for the past 20 years,

I am currently the CEO of a small company.

Key career highlights include

  • FPGA design using Verilog HDL

    • ISP ASIC development for CCTV (approx. 10 years)

    • OLED Display inspection equipment development (approx. 3 years)

    • Equipment development using FPGA

  • MCU FW

    • STM32

    • PIC32

    • AVR, ATMEGA

    • DSP (TI)

  • Windows Application Development

    • Visual Studio MFC, C++

.

More

Curriculum

All

103 lectures

Course Materials:

Lecture resources
Published: 
Last updated: 

Reviews

All

3 reviews

5.0

3 reviews

  • mjs1004님의 프로필 이미지
    mjs1004

    Reviews 5

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    Average Rating 5.0

    5

    100% enrolled

    Thank you for such a helpful lecture!

    • kyum5258802님의 프로필 이미지
      kyum5258802

      Reviews 6

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      Average Rating 4.7

      5

      30% enrolled

      • neulha님의 프로필 이미지
        neulha

        Reviews 15

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        Average Rating 5.0

        5

        31% enrolled

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