RISC-V CPU Design for FPGA Implementation ① Learning RV32I Instruction Structure and Execution Principles with Python

When people decide to build a CPU, they usually start by looking for a circuit diagram. However, the moment they unfold the schematic, unanswerable questions arise: Why must this block be here? Why are there two ports for reading registers? The answers all lie within the instructions. Once you know what an instruction requires, the necessary circuitry is determined. It doesn't work the other way around. There are already many RISC-V lectures available. However, most of them simply display values on a slide, say "This is how it works," and move on. Students have no way to verify if those values are correct. This course provides a Python-based instruction execution simulator. When you type `run ADD`, the machine code is assembled on the spot, the 32 bits are laid out by field, and you can see exactly how the registers change on your screen. Every number in the textbook is a result of this tool's execution, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators often have installation barriers. This tool only requires Python. You don't need a board, a license, or a complex setup. This is a process of executing all 40 RV32I instructions without skipping a single one, discovering for yourself what the circuit needs to do.