Introduction to FSM Design | From State Diagrams to Verilog-HDL 3-Process Implementation

Learn step by step, from the fundamental principles of the AMBA AXI4 protocol to Verilog RTL design, Vivado simulation verification, and FPGA implementation. Complete a 2-Master × 2-Slave interconnect through single read/write transactions, burst transfers, multi-master arbitration, and address decoding. Furthermore, develop the foundational hardware skills needed to design SoCs that connect RISC-V CPUs with memory, DMA, and peripherals, as well as to port FreeRTOS.

This is a free hands-on course where you implement a Systolic Array—the core parallel computing architecture of AI semiconductors—directly in Verilog and verify it through Vivado simulation. Using a 3×3 Output-Stationary structure as an example, you will learn step by step, from Processing Element design to input skewing, wavefront analysis, and testbench verification, enabling you to fully understand the fundamental computational principles of AI NPUs without an FPGA board.

You will systematically learn everything from the fundamentals of digital logic circuits to Verilog-HDL syntax, combinational and sequential logic circuit design, and verification through simulation. Drawing on 30 years of experience in Samsung Electronics’ semiconductor division, the instructor will help you clearly understand the relationship between HDL code and actual hardware operation and develop the ability to write synthesizable RTL code.

This course is a free program that guides you through setting up the AMD Vivado and Python development environments from scratch, as required for FPGA and NPU design projects.

Learn a system of 7 technical fields and 35 engineering roles developed by a semiconductor industry expert with 30 years of experience in Samsung Electronics’ Device Solutions (DS) Division, based on an analysis of recruitment materials from 19 global semiconductor companies. Understand the actual responsibilities and required competencies for each role—from design, processes, devices, and packaging to data analysis—explore career paths available for each major, and develop a job-preparation strategy. ※Lecture language: The lecture slides are provided in English, while the explanations are delivered in Korean. This format is designed to accurately convey the technical terms and job descriptions used in the JDs of global semiconductor companies.

As you study CPUs and RISC-V, you may understand what the instructions do but still find yourself asking, “How are these instructions actually executed in hardware?” and “How can I verify that a CPU I designed myself really works correctly?” Many existing resources stop at ISA explanations or simple CPU examples, and many others rely on completed IP, making it difficult to experience the entire process of designing and verifying a CPU yourself and running programs on an actual FPGA. I have spent many years working in R&D and business in the system semiconductor field, and I have observed this learning gap firsthand while teaching semiconductor design and FPGA at a university. For this reason, rather than providing a completed CPU and simply checking that it operates, this course is structured around designing the CPU directly in a White Box approach, starting with the question, “What hardware is required to execute RV32I instructions?” In Volume 3, we expand Volume 2’s TinyRV32I into a Full-Version 32-bit CPU that uses 40 RV32I instructions. We extend the datapath, Decoder, Branch·Jump, and Byte/Halfword Memory Access, and implement Forwarding and Load-Use Interlock so that the 5-stage Pipeline can handle data dependencies on its own. We then integrate CSR, Exception, Interrupt, Trap, and MRET to complete a CPU capable of handling not only normal program execution but also exceptions and external events. The design does not end with RTL Simulation. You will run actual programs on the CPU, compare the results with the Spike Reference Model, and learn the purpose of the RISC-V Architecture Compatibility Test as well as how to perform and evaluate it through real verification cases. Finally, you will implement the verified CPU on an Arty S7-25 FPGA, receive input from Switches and Buttons, run programs, and confirm the results by displaying them on LEDs. The problem this course aims to solve is not simply learning more RISC-V instructions. Its goal is to connect instructions → CPU architecture → Verilog RTL → Pipeline control → program execution → standards-based verification → actual FPGA operation into a single flow, enabling students to fundamentally understand the internal structure of a CPU and develop the engineering skills to design and verify one themselves.

Starting from the operating principles of RISC-V instructions, this is a hands-on CPU design course in which you directly design a 32-bit CPU with a five-stage pipeline, completing the process from Verilog RTL implementation and simulation verification to running it on a physical FPGA. Among the 40 RV32I instructions, 14 instructions essential for learning the core structure of a CPU are selected to progressively build TinyRV32I. You will directly design and verify the key structures that make up a real CPU, including the datapath, pipeline registers, ALU and control circuits, branches, hazards, stalls and flushes, and memory-mapped I/O. The Verilog RTL, testbenches, assembly programs, memory images, and FPGA constraint files used in the course are provided. Ultimately, you will run actual programs on an Arty S7-25 FPGA using the CPU you designed. This course does not end here. After completing the core CPU structure through TinyRV32I, the series continues as a step-by-step CPU design program in which you expand it into a Full RV32I CPU supporting all 40 RV32I instructions in the follow-up course.

Did you give up while learning Verilog and EDA tools? A semiconductor professor who designs NPUs himself will show you how to understand everything from CPUs to NPUs by calculating with just 9 Excel files.

When you decide to build a CPU, you usually start by looking for a circuit diagram. But the moment you unfold the schematic, questions arise that you cannot answer. Why does this block need to be here? Why are there two ports for reading registers? The answer lies entirely in the instructions. Once you know what the instructions require, the circuits you need are determined. It does not work the other way around. There are already many RISC-V courses. But most of them display values on slides, say "This is how it works," and move on. Students have no way to verify whether those values are correct. This course comes with a Python instruction-execution simulator. Type run ADD, and the machine code is assembled on the spot, the 32 bits are broken down by field, and how the registers change appears on the screen. Every number in the textbook is the result of running this tool, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators are difficult to install. This tool only requires Python. No board, license, or installation is needed. You will execute all 40 RV32I instructions yourself without leaving out a single one, discovering along the way what the circuit needs to do.

When you learn machine learning, you learn how to improve accuracy. But the moment you try to put that model onto an actual chip, questions no one has answered remain. How many multiplications does this model perform? How much does it need to remember, and for how long? Can the chip specifications you are targeting handle those requirements? Machine learning textbooks talk about accuracy, and semiconductor textbooks talk about circuits, but materials that bridge the gap between them are rare. I repeatedly encountered this gap while implementing RISC-V CPUs and NPUs on FPGAs. The model with the highest accuracy often turned out not to fit on the board. In this course, you will build six algorithms directly in Python, measuring the number of multiplications, comparisons, memory usage, and accuracy each time. Then you will convert those figures into the resources of an actual FPGA board. Saying that something requires a certain number of multiplications is not enough to gauge its size, but knowing that it uses a certain percentage of the board makes the decision clearer. After nine Labs, when the six models are brought together in a single table, an unexpected picture emerges. We spent nine lessons counting multiplications, but multiplications were not what held us back. After that, we reduce floating-point values to integers, manage bit widths, and even establish criteria for evaluating the circuit. You do not need an FPGA board. The course is conducted entirely in Python, and the board is used only as a reference for converting the measurements.

Putting a neural network on an FPGA—the phrase is familiar, but few have actually done it. If you want to stay a step ahead in capstone projects, competitions, or graduation projects, you must be able to go beyond just training a model and actually build and prove how those computations run inside a real chip. This course bridges that exact gap between theory and physical hardware. You will complete a neural network accelerator (NPU) for MNIST digit recognition from start to finish—from reading specifications to Python golden models, Verilog RTL design, and FPGA verification. From Conv layers made with line buffers and parallel MACs, through ReLU, MaxPool, and Flatten, to fully connected layers and Argmax—you will integrate nine blocks into a single chip and prove for yourself that "the Python reference and the hardware output do not differ by even a single bit (Bit-True)." I have even included how to overcome those frustrating moments when the simulation runs fine but the results are subtly different. I will guide you through practical know-how that general deep learning textbooks don't cover, such as integer quantization, array axis reordering, and accumulator overflow prevention. I have distilled the trial and error I experienced over years of RISC-V CPU design and FPGA Bit-True verification into this course so that you don't have to repeat them. By the end of the class, you will have a completed hardware project that allows you to say, "I designed and verified it myself."

To design AI semiconductors such as NPUs, transformer accelerators, and mini LLMs yourself, you need to understand theoretically why the computations inside them occur. This course distills and condenses into three parts only the essential theory required for hardware design, covering everything from a single neuron to CNNs, transformers, and LLMs. Rather than memorizing formulas, a professor with 30 years of experience in the semiconductor industry connects software theory with hardware implementation through an intuition for “why it works that way.”

This course is for those who have learned Verilog syntax but are stuck wondering, "So, what should I build?" With just a single FPGA board, you will directly design four types of hardware: a digital clock, an ultrasonic distance sensor, an OLED display, and real-time camera video. The difficulty progresses from output to input/control, display, and finally video, allowing you to master digital design through hands-on experience with visible results. An active professor with 30 years of experience in the semiconductor industry teaches only content that has been verified on actual FPGAs.

Many people have learned FPGA and Verilog but get stuck at the question, "So, how do I actually build an AI accelerator?" This course resolves that curiosity. Using just a single entry-level FPGA and free tools, you will start from a hand-designed 3×3 kernel, train a CNN yourself, quantize the trained weights to INT8 to load onto the hardware, and verify that the results are Bit-True—not deviating by even a single bit from the Python model. As a professor with 30 years of experience in the semiconductor industry, I teach only verified content as 'working circuits' on actual FPGAs. By gaining the experience of designing and proving it yourself rather than just learning theory, you will acquire practical skills that are recognized in the fabless design and AI semiconductor fields.