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Building an MNIST NPU with FPGA — From RTL to Bit-True Verification

Putting a neural network on an FPGA—the phrase is familiar, but few have actually done it. If you want to stay a step ahead in capstone projects, competitions, or graduation projects, you must be able to go beyond just training a model and actually build and prove how those computations run inside a real chip. This course bridges that exact gap between theory and physical hardware. You will complete a neural network accelerator (NPU) for MNIST digit recognition from start to finish—from reading specifications to Python golden models, Verilog RTL design, and FPGA verification. From Conv layers made with line buffers and parallel MACs, through ReLU, MaxPool, and Flatten, to fully connected layers and Argmax—you will integrate nine blocks into a single chip and prove for yourself that "the Python reference and the hardware output do not differ by even a single bit (Bit-True)." I have even included how to overcome those frustrating moments when the simulation runs fine but the results are subtly different. I will guide you through practical know-how that general deep learning textbooks don't cover, such as integer quantization, array axis reordering, and accumulator overflow prevention. I have distilled the trial and error I experienced over years of RISC-V CPU design and FPGA Bit-True verification into this course so that you don't have to repeat them. By the end of the class, you will have a completed hardware project that allows you to say, "I designed and verified it myself."

12 learners are taking this course

Level Intermediate

Course period Unlimited

Artificial Neural Network
Artificial Neural Network
Computer Vision(CV)
Computer Vision(CV)
Verilog HDL
Verilog HDL
FPGA
FPGA
verification
verification
Artificial Neural Network
Artificial Neural Network
Computer Vision(CV)
Computer Vision(CV)
Verilog HDL
Verilog HDL
FPGA
FPGA
verification
verification

What you will gain after the course

  • A complete Neural Processing Unit (NPU) project, from specification to RTL and verification, suitable for submission to capstone projects, competitions, and graduation projects.

  • The entire process of first fixing hardware constraints, training the neural network accordingly, quantizing the weights into integers, and porting them to hardware — the experience of building everything yourself from the training stage, rather than just using weights created by others.

  • Bit-True verification capability to directly prove that the Python reference and hardware output do not differ by even a single bit — the skill to turn "it seems to work" into "proven to be an exact match"

  • Design capability to directly implement Conv, ReLU, MaxPool, Flatten, Fully Connected, and Argmax in Verilog RTL (including line buffers, parallel MACs, and accumulators)

  • Know-how for handling practical pitfalls such as axis order conversion, scale adjustment, and accumulator overflow prevention encountered when converting trained floating-point weights to integers.

  • System integration experience in integrating and verifying individual blocks into a single chip.

  • The first step of NPU ISA design to expand fixed accelerators into instruction-based processors

Building neural networks as chips, not software.

From specification to RTL and verification, design an MNIST recognition NPU yourself and prove it down to a single bit.


Have you ever had these concerns?

You've trained models, but no one teaches you how to actually deploy them onto an FPGA. You've worked with Verilog, but you've never completed an entire neural network as a single accelerator. You've chosen "AI Hardware" as your capstone or graduation project topic, but you're at a loss as to where to begin. You converted floating-point weights to integers, and while the simulation runs, the results are strange. You've confirmed that "it seems to work," but you don't know how to prove it's actually correct.


The answer this course provides

This course builds a Neural Processing Unit (NPU) for MNIST digit recognition from scratch, covering everything from reading specifications to Python golden models, hardware-constrained training and integer quantization, Verilog RTL design, and FPGA bit-true verification without skipping a single step.

By the end of the course, you will have a completed hardware project in your hands that can be submitted as-is for capstone projects, competitions, and graduation projects. And you will be able to say, "I trained it, designed it, and verified it myself, down to the very last bit."


The cheat code unique to this course

First, hardware comes first, followed by training. Instead of using weights created by others, you first fix hardware constraints such as bit width and operation order, and then train the neural network yourself to fit those constraints. The Python model becomes the bit-level blueprint for the RTL.

Second, we change "it seems to work" to "it matches exactly." We put Bit-True verification, which proves that the Python integer golden model and the RTL output do not differ by even a single bit, at the forefront. We convey the pitfalls of practical work, including why it is easy to be deceived if only the classes match and why large-scale verification is necessary.

Third, we move from accelerators to processors. It doesn't stop at a single example; we open the path for you to expand a fixed accelerator into an instruction-controlled processor (NPU ISA).


Curriculum at a glance (7 sections · 10 lectures · 7 hours 7 minutes)

Section 1. The Language of Design — How to Read MNIST NPU Specifications
Section 2. Python — Hardware Reference (Golden Model), Training, and Integer Quantization
Section 3. Feature Extraction Circuits — Line Buffers and 4-Channel Parallel MAC
Section 4. Transformation and Decision Circuits — ReLU, MaxPool, Flatten, Fully Connected, and Argmax
Section 5. Integration and Verification — Nine Blocks into One Chip, Proving with Bit-True
Section 6. Expansion — NPU ISA and Mini Compiler
Section 7. Setting Up the Practice Environment — Must Check Before Simulation


Recommended for

This course is recommended for undergraduate students preparing capstone or graduation projects on AI hardware, competition participants in need of standout results, working engineers at design firms looking to expand their expertise into NPUs and AI accelerators, self-motivated hardware engineers seeking the experience of building and verifying that theory books alone cannot provide, and prospective graduate students aiming for a career in NPU design.


Prerequisites

Basic knowledge of Verilog HDL and digital logic design is sufficient. For Python, being able to read and run code is enough, and you don't need to know deep learning theory — neural network operations are explained from scratch from a hardware perspective. Even if you are new to FPGA tools, Section 7 provides guidance on setting up the environment.

Recommended for
these people

Who is this course right for?

  • Professional hardware engineers currently working at semiconductor or design firms who want to expand their capabilities into AI accelerator and NPU design — those who are familiar with RTL design but need experience in completing and verifying a neural network as a full accelerator.

  • Self-development-oriented engineers who want to steadily improve their skills even amidst busy work — those who want practical projects that go beyond theory books, where they build and prove results with Bit-True.

  • Undergraduate students majoring in electronics, electrical engineering, or semiconductors who have chosen "AI Hardware" as their capstone or graduation project topic, but feel lost on how to convert neural networks to RTL and implement them on an FPGA.

  • Participants in competitions who need results that stand out — those who want to showcase an "NPU designed personally and proven with Bit-True" rather than just model training.

  • Prospective graduate students aiming for a career in NPU/AI accelerator design who need implementation and verification experience rather than just theory.

Need to know before starting?

  • This course is intended for those who have a basic understanding of Verilog HDL and digital logic design.

  • Basic Python syntax is sufficient as long as you can read and execute the golden model code.

  • Experience with FPGA simulation tools is a plus.

Hello
This is EdgeChipLab

Career Verified

Design and implement AI semiconductors directly on FPGAs

As a current university professor, I have incorporated 30 years of experience in the system semiconductor industry and expertise in AI semiconductor research and education.

This is a practical curriculum directly designed and verified on an FPGA by a professor who began as a systems semiconductor researcher in Samsung Electronics’ DS Division, went on to serve as a Director at Samsung’s UK and Germany subsidiaries, and later led the System LSI marketing and sales group before becoming a professor teaching semiconductor engineering.

This is not simply a course on how to use FPGAs.
It is designed to help you understand AI algorithms → directly design NPUs and CPUs in RTL → implement them on an FPGA → verify them on actual hardware → and ultimately expand to AI SoCs.

AI Algorithm → RTL Design → FPGA Implementation → Bit-True Verification → AI SoC

 

Beyond theory to real-world AI hardware implementation

It is difficult to develop system-level AI semiconductor design capabilities with only scattered, fragmented knowledge.

Learners do not stop at using completed black-box IP. The goal is to progressively develop the system design skills to design AI NPUs and RISC-V CPUs themselves, integrate memory and peripherals, and ultimately build their own AI SoC.

Starting with the fundamentals of transistors and digital circuits, you will progress through FPGAs, CPUs, and NPUs to hardware for accelerating Transformers and LLMs.

 

We validate the research results on actual FPGA hardware.

This is not a lecture you only watch. Rather than stopping at theory or simple simulations, you will run AI semiconductor circuits you designed yourself on an actual FPGA and perform Bit-True verification, confirming that the Python model and RTL results match down to the last bit.

We also connect the instructor’s research results, including four KCI-indexed papers on AI semiconductors, FPGAs, and RISC-V, with the educational content, applying technologies validated through research to actual design and FPGA implementation.

We provide source code essential for hands-on practice, including our self-developed RISC-V CPU, Python code for image training, and Verilog RTL.

Centered around the affordable Arty S7-25 FPGA board and the free Vivado design tool, this course is designed to allow learners to reproduce the entire process of designing, implementing, and verifying their own work.

It can also be used with Digilent FPGA boards, including the Zybo Z7. You just need to modify the XDC pin mapping (board) and clock division parameters (RTL) to match the board.

The “MNIST NPU with FPGA” course only requires modifying the XDC pin mapping, while the courses using the OLED and Camera require modifying the clock division parameters (RTL).

→The course exercises are configured with clock division parameters based on Arty S7’s 100 MHz input clock. Since other boards have different input clocks (for example, Zybo Z7 has 125 MHz), you will need to recalculate the division values so that the target frequency remains the same. If you miss this point, the display or video may not output properly, which can easily be mistaken for a code error, so please check this.

 

A seamless full-stack roadmap: from the basics to a mini LLM accelerator

Every lecture is not an isolated fragment, but part of a journey toward completing one vast system.

  • Step 1: AI Theory and Image Processing Fundamentals (including Machine Learning)

  • Step 2: AI Accelerator (NPU) Design and Verification (Including Machine Learning)

  • Step 3: RISC-V CPU Design and System Integration

  • Step 4: Advanced AI SoC Implementation and Expansion into a mini LLM Acceleration Platform (Continuous Content Updates)

     

 

Objective verification metrics

All design deliverables from this course have undergone rigorous validation against global standards and by the academic community.

  • RISC-V Architecture Verification: In-house developed RISC-V CPU, passed the International Foundation’s official compliance test (ACT), and source code released (GitHub)

  • Academic Authority: Four Sole-Author Academic Papers (published in the prestigious KCI A-ranked journal IJIBC)

  • Global Recognition: Published four global Amazon technology books (reached #1 bestseller status)


    Published books: Roger Kim: books, biography, latest update

  • Real-World Operation Verification Complete: Core IPs, including the RV32I CPU, NPU, vision system, GPS, Transformer, and AURA-Edge SoC, operate flawlessly in the Arty S7 environment.

     

Take on the challenge. By the time you complete this process of uploading code to the board yourself and checking the results, you will have leveled up into a hardware engineer with a completely different perspective than before.

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Curriculum

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10 lectures ∙ (4hr 39min)

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