
Verilog FPGA Program 5 (Serdes)
alex
Implement LVDS (Serdes) in FPGA.
Intermediate
FPGA, verilog
Through this lecture, you can implement a DDR Controller using FPGA.


Reviews from Early Learners
5.0
mjs1004
I was overwhelmed when trying to use the DDR Controller, but this course does a great job of teaching the essential parts I needed. I was struggling with where to start and how to read Xilinx's documentation, but after taking the course, I feel like I can see the path forward. Thank you for the excellent course.
5.0
coldugs
I think it is difficult to find FPGA-related materials, and even if you do find them, they are so extensive that it is difficult to learn. It was a great help to have such good materials.
5.0
miheungsound
I think this lecture will be very helpful. I am watching it over and over again. Thank you.
DDR Controller
Frame Buffer
DDR Memory Controller skills required for a proficient Verilog developer!
✨
Many functions are provided in the form of IP within FPGAs. Among them, this explains the DDR Controller, which is primarily used for processing video data.
1. Implement exactly according to the datasheet
2. Implementation using IP provided by Xilinx
The author experienced many of these difficulties while implementing the DDR Controller. I often thought it would be great to have a single document that summarizes only the necessary parts. It is more efficient to first understand only the essential components to proceed with development and try reading/writing to the DDR, and then gradually deepen your understanding. It is effective to understand the overall structure first and then delve into the details later. This book is structured so that even developers encountering the DDR Controller for the first time can easily approach it.
DDR Memory is very important in video data processing. However, it is difficult to access unless you are an expert, and the reality is that there is very little material covering such professional content. This course covers everything about implementing a DDR Memory Controller. It also explains in detail how to implement a Frame Buffer using a DDR Controller.
💾 Please check before taking the course!
There are very few documents that cover the DDR Memory Controller. This lecture explains the entire process in detail. It covers everything from the process of creating and simulating Memory IP to implementing a universally applicable DDR Memory Controller and a Frame Buffer for video data processing. Furthermore, it is structured so that you can verify and understand the operation of each source code through simulation.
If you fully understand the contents of this course, you will not only be able to implement a DDR Controller but also become a skilled developer in FPGA implementation using Verilog.
For those looking to learn Verilog, the DDR Memory Controller is an excellent skill to acquire. Even many individuals with extensive development experience have never encountered a DDR Memory Controller. This provides an opportunity to take your Verilog skills to the next level.
For those who purchase this course, all source codes explained in the lectures will be provided. The provided materials consist of code that was written from scratch and verified step-by-step during the creation of this course. Furthermore, the code is structured to be immediately applicable in professional field environments. We hope you become a master of DDR Controllers through this course.
This lecture covers the process of creating a DDR Controller IP and understanding its operation through Simulation to see how the generated IP functions, and involves designing a versatile DDR Controller using the created IP. Finally, it explains the process of implementing a Frame buffer for image data processing.
This course was structured based on the author's long-standing experience in ISP (Image Signal Processing) development. The contents of this book consist of code that can be applied directly to practical work. Although some parts may be somewhat difficult, please read through the parts you don't understand about 2-3 times, and review the operations while simulating the code.
This course conducts practice sessions using the Arty A7 development board sold by Digilent and the HIL-A25T board sold by our company. When dealing with FPGAs, it is very important to apply designs to actual hardware and verify the results. There are limits to what can be implemented through simulation alone. Verification must be performed on hardware. (Regarding the frame buffer covered in the final chapter of this book, it is unfortunate that verification was conducted only through simulation as a suitable hardware could not be found. I look forward to finding an appropriate board in the future to proceed with hardware verification.)
Chapter 1 is an overview of the overall content.
Chapter 2 explains the Arty A7 board used in the practice.
Chapter 3 explains how to generate the DDR Controller IP and discusses the User Interface Logic.
Chapter 4 covers understanding the operational characteristics through simulation of the generated DDR Controller IP. This is very important for implementing a versatile DDR Controller.
Chapter 5 implements a universally usable DDR Controller and , uses it to implement Read/Write operations across the entire range of the DDR Memory. Additionally, it generates a Bitstream to verify the results on the board.
Chapter 6 examines Memory Access speed, and covers content for implementing maximum speed.
Chapter 7 implements a Frame Buffer for video data processing using the general-purpose DDR Controller implemented in Chapter 5.
Chapter 8 implements a 32-bit interface using two 16-bit DDR memories.
Chapter 9 implements a DDR Controller on Spartan6.
Chapter 10 implements the DDR4 Controller.
Watch the previous lecture together 👀
add_shortcode('course','329685','list')
Q. Is it possible for Verilog beginners as well?
You must have a basic knowledge of Verilog. It may be difficult if you do not have the relevant knowledge.
Q. Are there any prerequisites?
The Arty A7 board is used to implement and verify the code. Once the board is ready, you can directly check the implemented content. However, since all sources are configured to be simulatable, you can listen to the lectures first and verify them later once the board is prepared.
Q. Which program tool is used?
We use Xilinx Vivado 2018.3. Any version from 2018.3 or later will work.
I have worked as a developer in large corporations and SMEs for over 20 years and currently run a small business. I have developed ISP (Image Signal Processing) ASICs for CCTV and numerous products using FPGAs, such as OLED inspection equipment and DAQ (Data Acquisition Systems). Beyond FPGAs, I have extensive experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming. Based on the wide range of experience I have accumulated, I hope to be of help to your learning.
Who is this course right for?
Image data processing using FPGA
Frame Buffer Implementation
Those who want to learn Verilog
For those who want to learn FPGA
Need to know before starting?
Verilog
vivado
FPGA
Career Verified
1,791
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96
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4.8
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Courses
I have worked as a developer at both large corporations and SMEs for the past 20 years,
I am currently the CEO of a small company.
Key career highlights include
FPGA design using Verilog HDL
ISP ASIC development for CCTV (approx. 10 years)
OLED Display inspection equipment development (approx. 3 years)
Equipment development using FPGA
MCU FW
STM32
PIC32
AVR, ATMEGA
DSP (TI)
Windows Application Development
Visual Studio MFC, C++
.
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277 lectures
Course Materials:
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7 reviews
5.0
7 reviews
Reviews 5
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Average Rating 5.0
Edited
5
I was overwhelmed when trying to use the DDR Controller, but this course does a great job of teaching the essential parts I needed. I was struggling with where to start and how to read Xilinx's documentation, but after taking the course, I feel like I can see the path forward. Thank you for the excellent course.
Reviews 4
∙
Average Rating 5.0
5
It helped me a lot
Thank you for your help. Have a nice day today too. ~!!
Reviews 1
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Average Rating 5.0
5
I think it is difficult to find FPGA-related materials, and even if you do find them, they are so extensive that it is difficult to learn. It was a great help to have such good materials.
When I first started learning, I was also confused about what to look at and how to start. I will try to make it more useful. Thank you~!!
Reviews 2
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Average Rating 5.0
Reviews 2
∙
Average Rating 5.0
5
I think this lecture will be very helpful. I am watching it over and over again. Thank you.
Thank you. I hope you fully understand the DDR controller through this lecture. If you conquer one IP provided by Xilinx, it will be of great help in using other IPs. The FPGA field is not an easy field. I hope you complete it to the end~!!
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