Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

Name: Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)
Price: 110000 KRW

Through this lecture, you will be able to implement a DDR controller using FPGA.

(5.0) 6 reviews

115 learners

alex

verilog

베릴로그

fpga

FPGA

Reviews from Early Learners

What you will learn!

DDR Controller
Frame Buffer

What a skilled Verilog developer needs
DDR Memory Controller Skill! ✨

Implemented with FPGA
DDR Memory Controller 🛠️

FPGAs provide many functions in the form of IP. Among them, we will explain the DDR Controller, which is mainly used to process image data.

Implementing DDR Controller
Two ways 🤔

1. Implement as per the data sheet

This is a method mainly used by people with long experience.
As the system becomes more complex, implementing it in code one by one is not easy. So, in many cases, only the necessary parts are implemented and used, but there is the difficulty of having to implement it differently every time the project changes.

2. Implementation with IP provided by Xilinx

This is a general-purpose IP. Once you learn how to use it, you can use it for multiple projects without making any major changes.
It's not easy to learn how to use it at first. Xilinx provides a lot of documentation and sample code, but there is so much information that it's hard to use it.

The author experienced many of these difficulties while implementing DDR Controller. I thought it would be good to have a single document that only organizes the necessary parts. It is efficient to first understand only the necessary parts, proceed with development, read/write DDR, and gradually increase your understanding. It is effective to first understand the overall structure, and then understand the details later. This book is organized so that even developers who are new to DDR Controller can easily approach it .

DDR Memory is very important in image data processing. However, it is difficult for non-experts to approach, and there are few materials covering this specialized subject. This lecture covers all the contents of implementing DDR Memory Controller . It also explains in detail how to implement Frame Buffer using DDR Controller.

💾 Please check before taking the class!

This lecture is a text lecture in PDF format and does not provide separate videos.
We provide source code for the mods described in the lecture.
We will be practicing on the Arty A7 development board sold by Digilent.

Lecture Features ✨

#1.
DDR Controlle's
I've got everything

There are few documents that cover DDR Memory Controller. This lecture explains all the processes in detail. It explains all the processes from creating and simulating Memory IP to implementing DDR Memory Controller for general use and implementing Frame Buffer for image data processing. In addition, each source code is configured so that you can verify it through simulation and understand its operation.

If you understand all the contents of this lecture, you will become a capable developer who can not only implement DDR Controller but also implement FPGA using Verilog.

#2.
Verilog skills
Try upgrading

For those who want to learn Verilog, DDR Memory Controller is a very good skill. There are many people who have a lot of development experience but have not encountered DDR Memory Controller. We provide an opportunity to upgrade Verilog to the next level.

#3.
Applicable to practice
Provide source code

For those who purchase this course, we will provide all the sources explained in the course. The sources provided are composed of materials that have been coded and verified from the beginning while producing the course. In addition, they are composed of codes that can be used immediately in the field. We hope that you will become a master of DDR Controller through this course.

What you'll learn 📚

This lecture explains the process of creating DDR Controller IP and how the created IP operates through simulation to understand the operating process , and design a DDR Controller that can be used universally using the created IP . Finally, it explains the process of implementing a Frame Buffer for processing image data .

This lecture is based on the author's experience in developing ISP (Image Signal Processing) for a long time . The contents of this book are codes that can be applied directly to practical work . The contents may include some difficult parts , but please read the parts you do not understand 2-3 times and review the operation contents while simulating the codes.

This lecture will be conducted on the Arty A7 development board sold by Digilent. When dealing with FPGA, it is very important to apply it to HW and check the results. There are limits to implementing it through simulation. It must be verified on HW. (It is regrettable that the content on the frame buffer covered in the last chapter of this book was verified only through simulation because we could not find a suitable HW. We hope to find a suitable board in the future and proceed with HW verification.)

Chapter 1 is an overview of the overall content.

Chapter 2 describes the Arty A7 board used for the exercises .

Chapter 3 explains how to create DDR Controller IP and User Interface Logic .

Chapter 4 understands the operational characteristics of the generated DDR Controller IP through simulation . This is very important for implementing a DDR Controller that can be used for general purposes .

Chapter 5 implements a general-purpose DDR Controller and implements Read/Write across the entire DDR Memory area . It also generates a Bitstream and checks the results on the board .

Chapter 6 looks at Memory Access speed and covers how to achieve maximum speed .

Chapter 7 implements a Frame Buffer for video data processing using the general-purpose DDR Controller implemented in Chapter 5 .

Chapter 8 implements a 32-bit interface using two 16-bit DDR memories.

Chapter 9 implements the DDR Controller in Spartan6.

Chapter 10 implements the DDR4 Controller.

Detailed Curriculum (Table of Contents)

outline
HW configuration
1. How to use USB-JTAG
2. JTAG-HS2 (or JTAG-HS3) connector
Generate DDR Controller IP
1. Create a project
2. Create Memory IP
3. Memory IP Structure
4. User Interface Block
5. User Interface Signals
6. User Interface Timing
Simulation
1. Simulation Environment Settings
2. Simulation
3. Check simulation results
Implementing User Interface Logic
1. outline
2. Write Module Implementation
3. Read Module structure
4. Implementing User Interface module (ddr_test module)
5. mig_top Module Implementation
6. Top Module Implementation
7. Top Module Simulation
8. Bitstream Generation
9. Bitstream Download & Verify
DDR3 Memory Access Speed
1. mig7_write8 fix
2. mig7_read8 fix
3. mig7_write_top fix
4. mig7_read_top fix
5. Fix ddr_test
6. Modify define.v
7. MIG7 Memory Interface IP Modification
8. clk_gen fix
9. Arty35Top.v edit
10. Generate Bitstream and Check Results
Frame Buffer Implementation
1. Data Preparation
2. Image Decoder
3. Frame Buffer Overview
4. frame_write
5. frame_read
6. Checking Frame Buffer using video data
Implementing 32bits Interface
1. Create a project
2. Create Memory IP
3. Understanding IP behavior generated through simulation
4. User Interface Implementation
5. mig32_top module simulation
6. conclusion
Spartan6 DDR Controller Implementation
1. Create a project
2. IP creation
3. mcb review
4. Verify operation through simulation
5. Code implementation
6. Full range read/write implementation
7. conclusion
DDR4 Controller Implementation
1. Create a project
2. IP creation
3. simulation
4. Code implementation
5. Address related
6. xdc generation
7. Check the results
8. conclusion
References
Revision History

See previous lectures together 👀

Expected Questions Q&A 💬

Q. Is it possible for Verilog beginners?

You should have basic knowledge of Verilog. Without it, it can be difficult.

Q. Is there anything to prepare?

We use the Arty A7 board to implement and verify the code. Once the board is ready, you can check the implementation yourself. However, since all sources are configured to be simulated, you can listen to the lecture first and verify it later when the board is ready.

Q. What program tools do you use?

I'm using vivado 2018.3 from Xilinx. Any version later than 2018.3 should work.

Introducing the knowledge sharer ✒️

I have been working as a developer for over 20 years in large and small companies and currently run a small business. I have developed an ISP (Image Signal Processing) ASIC for CCTV and many products using FPGA such as OLED inspection equipment and DAQ (Data Acquisition System). In addition to FPGA, I have a lot of experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, Windows Program, etc. I hope that my extensive experience will be helpful to your learning.

Recommended for
these people

Who is this course right for?

Image data processing using FPGA
Frame Buffer Implementation
If you want to learn Verilog
If you want to learn FPGA

Need to know before starting?

Verilog
alive
FPGA

Hello
This is

1,677

Learners

Reviews

125

Answers

4.8

Rating

Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

Verilog HDL을 이용한 FPGA 설계
- CCTV용 ISP ASIC 개발 (약 10년)
- OLED Display 검사장비 개발 (약 3년)
- FPGA를 이용한 장비 개발
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Program
- Visual Studio MFC, C++

입니다.

Curriculum

All

277 lectures

Course Materials:

Lecture resources

Section 1. outline

7 lectures

Section 2. HW configuration

4 lectures

8. HW Configuration - 0
9. HW Configuration - 1
10. HW Configuration - 2
11. HW Configuration - 3

Section 3. Generate DDR Controller IP

25 lectures

12. Generate DDR Controller IP - 0
13. Generating DDR Controller IP - 1
14. Generating DDR Controller IP - 2
15. Generating DDR Controller IP - 3
16. Generating DDR Controller IP - 4
17. Generating DDR Controller IP - 5
18. Generating DDR Controller IP - 6
19. Generating DDR Controller IP - 7
20. Generate DDR Controller IP - 8
21. Generating DDR Controller IP - 9
22. Generate DDR Controller IP - 10
23. Generating DDR Controller IP - 11
24. Generating DDR Controller IP - 12
25. Generating DDR Controller IP - 13
26. Generating DDR Controller IP - 14
27. Generating DDR Controller IP - 15
28. Generate DDR Controller IP - 16
29. Generating DDR Controller IP - 17
30. Generating DDR Controller IP - 18
31. Generating DDR Controller IP - 19
32. Generate DDR Controller IP - 20
33. Generating DDR Controller IP - 21
34. Generating DDR Controller IP - 22
35. Generating DDR Controller IP - 23
36. Generating DDR Controller IP - 24

Section 4. Simulation

11 lectures

Section 5. Implementing User Interface Logic

44 lectures

Section 6. DDR3 Memory Access Speed

13 lectures

Section 7. Frame Buffer Implementation

32 lectures

Section 8. Implementing 32Bits Interface

32 lectures

Section 9. Spartan6 DDR Controller Implementation

83 lectures

Section 11. etc

4 lectures

Published:

Last updated:

Reviews

All

6 reviews

5.0

6 reviews

kwonjisu2159091
Reviews 1
∙
Average Rating 5.0
5
5% enrolled
I think it is difficult to find FPGA-related materials, and even if you do find them, they are so extensive that it is difficult to learn. It was a great help to have such good materials.
- ihil
  Instructor
  When I first started learning, I was also confused about what to look at and how to start. I will try to make it more useful. Thank you~!!
miheungsound8323
Reviews 2
∙
Average Rating 5.0
5
30% enrolled
I think this lecture will be very helpful. I am watching it over and over again. Thank you.
- ihil
  Instructor
  Thank you. I hope you fully understand the DDR controller through this lecture. If you conquer one IP provided by Xilinx, it will be of great help in using other IPs. The FPGA field is not an easy field. I hope you complete it to the end~!!
kimjw0319
Reviews 2
∙
Average Rating 5.0
5
100% enrolled
This is well organized content.
appleid71335256
Reviews 4
∙
Average Rating 5.0
5
57% enrolled
It helped me a lot
- ihil
  Instructor
  Thank you for your help. Have a nice day today too. ~!!
neulha
Reviews 14
∙
Average Rating 5.0
5
100% enrolled
When I was working on MCU, I didn't have much trouble with RAM (because there are abundant resources these days). However, as I was studying HW while working on FPGA or Zynq, I started to worry about RAM and had a lot of difficulties. This lecture was a great help. Please continue to provide good lecture materials~!
- ihil
  Instructor
  Thank you for your course review. The MCU environment and the FPGA development environment seem to be very different. Maybe they are different worlds. Thank you for helping me with the course. I hope you become a happy and capable developer. Thank you ~!!

$84.70

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Reviews from Early Learners

What you will learn!

Implemented with FPGA DDR Memory Controller 🛠️

Lecture Features ✨

#1. DDR Controlle's I've got everything

#2. Verilog skills Try upgrading

#3. Applicable to practice Provide source code

What you'll learn 📚

Expected Questions Q&A 💬

Introducing the knowledge sharer ✒️

Recommended for these people

HelloThis is .css-1q3zd4q{text-decoration-line:underline;text-underline-position:under;text-underline-offset:1px;}

Curriculum

Reviews

alex's other courses

Similar courses

Implemented with FPGA
DDR Memory Controller 🛠️

#1.
DDR Controlle's
I've got everything

#2.
Verilog skills
Try upgrading

#3.
Applicable to practice
Provide source code

Recommended for
these people

Hello
This is