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Verilog ZYNQ Program 1 (Zynq mini 7020)

This lecture is about using the Xilinx ZYNQ board. If you understand the contents of this lecture, you will learn the skills to understand Embedded_SW + User_Logic and apply them to practice.

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  • alex
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verilog
zynq
Verilog HDL
FPGA
vivado

What you will learn!

  • Verilog coding

  • Utilizing ZYNQ Board

  • How to use Vivado, Vitis

  • PS area, PL area implementation

  • Embedded fw + User Logic

Into the new world of ZYNQ
Give it a try!

📢 Please note before taking the class.

  • This course is a text lecture, approximately 80,000 characters long, in electronic document (PDF) format. All source files covered in the course will be provided to those taking the course. The course source code can be downloaded from Section 0 [Material Sharing Link].

Lecture Features ✨

#1.
I wanted to learn Zynq
For everyone.

Professional technical resources covering Zynq are virtually non-existent. While Xilinx does provide resources, the sheer number of documents makes it difficult to know which ones to read. This course provides a detailed explanation of Zynq fundamentals and how to apply them to practical projects. You can download and run all the examples directly on the practice board (Zynq mini 7020), making learning even more enjoyable. If you fully understand the content of this course, you'll acquire skills that can be immediately applied to real-world projects. We encourage you to explore the new world of Zynq.

#2.
Easy even for beginners
Gain practical knowledge.

The lecture content is organized as an electronic document (PDF), which is helpful for repeated study. You can download and review all lecture content on the practice board (Zynq mini 7020). Detailed instructions on tool setup and usage are provided, making it easy for even beginners to follow along. The ultimate goal of the course is to develop practical application skills. If you fully understand the lecture content, you'll be able to take charge of projects in your field.


Using Verilog
Using ZYNQ

This is the first lecture of Using ZYNQ with Verilog . All contents of this lecture are designed to be practiced on the “Zynq mini 7020” board . If you purchase the lecture, you can download and use all sources explained in the lecture from the data room . The source materials in the data room are composed of sources that were verified one by one by creating a project by chapter when this lecture was created .

ZYNQ is an FPGA released by Xilinx for Soc (System on Chip) . It contains an ARM Processor inside the FPGA . Users can implement the Arm Core Processor and User Logic with a single chip . Embedded SW and User Logic can be configured with a single chip without having to use a separate external Processor .

The ultimate goal of this lecture is to acquire the technology to configure “Embedded_SW + User_Logic” when carrying out a project using ZYNQ . If you fully understand the contents of this lecture , you will be able to design and implement most projects using ZYNQ . Rather than trying to understand the contents of this lecture just with your eyes , please create a project yourself according to the contents explained in the lecture, implement the code, download it to the board, and check the result . The world of FPGA is not a world that can be learned by understanding with your eyes . You will learn little by little by programming it yourself, downloading it to the board, and checking the result . If you want to understand with your eyes, it is better to watch the video lecture .

Detailed Curriculum
  1. outline
  2. HW configuration
    1. Board configuration
    2. Bank structure
    3. MIO (Multiplexed IO)
    4. Circuit diagram
      1. Bank500
      2. Bank501
      3. Bank502
      4. Bank34
      5. Bank35
  3. SW installation
  4. Basic Template Implementation
    1. Create a project
    2. Create Block Design
  5. Download the program
    1. Download in Debug Mode
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    2. Download using FSBL
      1. Create a project
      2. Add PL logic
      3. Bitstream generation
      4. FSBL implementation
      5. Create Boot Image
      6. Download and check results
    3. Download using FSBL, Application SW
      1. Create an FSBL project
      2. Create an Application Project
      3. Create Boot Image
      4. Download and check results
  6. GPIO
    1. GPIOPS implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    2. Interrupt implementation
      1. Download and check results
    3. AXI GPIO implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
    4. AXI GPIO Interrupt Implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
  7. Timer
    1. Create a project
    2. Application sw implementation
    3. Download and check results
  8. Interrupt
    1. Create a project
    2. Application sw implementation
    3. Interrupts Analysis
    4. Download and check results
  9. PS-PL interface
    1. Block Memory Interface
      1. Create a project
      2. Add PL logic
      3. Application sw implementation
      4. Download and check results
    2. PS-PL interface implementation
      1. Create a project
      2. PL User Logic Implementation
      3. Application sw implementation
      4. Download and check results
    3. User Interface Implementation
      1. Create a project
      2. Application sw implementation
      3. Download and check results
  10. Revision History

Q&A 💬

Q. Who is the target audience for this lecture?

This course is for those who want to learn about Xilinx Zynq. Even if you're new to Zynq, following the lectures will allow you to learn most of the Zynq concepts and apply them to your work.

Q. Is there anything I need to prepare to attend the lecture?

All content in this course uses material verified on the Zynq mini 7020 board. You will need a Zynq mini 7020 board and the Vitis 2022.1 tool before attending.

Q. What programming language do you use?

We use Verilog HDL, which is mainly used in companies.


Accumulated with 25 years of experience
We share our know-how on utilizing Verilog.

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming.

💾 Please check the lecture environment.

  • The training board is the Zynq mini 7020 (or 7010) . You can purchase it from Alina or other domestic shopping malls.
  • Windows OS environment, using Vivado 2022.1 .
  • This lecture is a text lecture in electronic document (PDF) format (approximately 80,000 characters/220 pages).

Recommended for
these people

Who is this course right for?

  • Anyone interested in Verilog programming

  • Anyone interested in FPGA

  • Anyone interested in ZYNQ

Need to know before starting?

  • C language

  • Verilog language

Hello
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Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

  • Verilog HDL을 이용한 FPGA 설계

    • CCTV용 ISP ASIC 개발 (약 10년)

    • OLED Display 검사장비 개발 (약 3년)

    • FPGA를 이용한 장비 개발

  • MCU FW

    • STM32

    • PIC32

    • AVR, ATMEGA

    • DSP (TI)

  • Windows Application Program

    • Visual Studio MFC, C++

입니다.

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219 lectures

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