etc. (Programming)

Verilog FPGA Program 6 - DDR Arbiter (Arty A7-35T)

Name: Verilog FPGA Program 6 - DDR Arbiter (Arty A7-35T)
Price: 110000 KRW

This lecture implements DDR Memory Arbiter.

(5.0) 1 reviews

9 learners

alex

ddrarbiter구현

fpga

verilog

텍스트 강의

FPGA

Verilog HDL

What you will learn!

DDR Arbiter
Image Frame Buffer

This lecture covers implementing the arbiter, the final stage of a DDR memory controller. When using DDR as a frame buffer for image data, DDR access (read/write) can overlap. This typically occurs when the input and output frame rates differ. In such cases, you need to design an arbiter to control access (read/write) timing. You must ensure that read and write requests are processed sequentially.

This lecture will implement a DDR arbiter to ensure sequential DDR access without overlapping when the input and output image frame rates differ. The results will be downloaded to the board and verified to be operational.

The structure of the text is as follows.

Chapter 2 describes the Arty A7-35T board used in the lab.

Chapter 3 describes the general system configuration.

Chapter 4 implements the program module by module.

Chapter 5 implements the Top Module and verifies the results through simulation.

Chapter 6 generates a bitstream and checks the results on the board.

💾 Please check before taking the class!

This lecture is a text lecture in PDF format and does not provide separate videos.
We provide the source code for the mods described in the lecture.
We will be conducting our hands-on training on the Arty A7 development board sold by Digilent.

Introducing the Knowledge Sharer ✒

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming. I hope my extensive experience will be helpful to you in your learning.

Recommended for
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Who is this course right for?

Anyone who wants to learn Verilog
Those who wish to learn FPGA
Want to learn ddr Arbiter?

Need to know before starting?

verilog
Vivado
xilinx fpga

Hello
This is

1,657

Learners

Reviews

124

Answers

4.8

Rating

Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

Verilog HDL을 이용한 FPGA 설계
- CCTV용 ISP ASIC 개발 (약 10년)
- OLED Display 검사장비 개발 (약 3년)
- FPGA를 이용한 장비 개발
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Program
- Visual Studio MFC, C++

입니다.

Curriculum

All

103 lectures

Course Materials:

Lecture resources

Section 1. Overview

4 lectures

Section 2. Hardware Configuration

4 lectures

5. HW Config - 0
6. HW Configuration - 6
7. HW Configuration - 7
8. HW Configuration - 8

Section 3. System Configuration

3 lectures

Section 4. Program Implementation

69 lectures

Section 5. Top Module Implementation

13 lectures

Section 6. Bitstream Generation and Result Verification

8 lectures

Section 7. Other

2 lectures

Published:

Last updated:

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1 reviews

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1 reviews

neulha
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Average Rating 5.0
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31% enrolled

$84.70

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