Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

Name: Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
Price: 110000 KRW
Rating: 4 (3 reviews)

Through this lecture, you will be able to implement a DDR Controller using FPGA.

(4.0) 3 reviews

35 learners

alex

텍스트 강의

verilog

하드웨어

Verilog HDL

FPGA

What you will gain after the course

DDR Controller
Frame Buffer
Verilog HDL

FPGA Design by someone with over 20 years of experience 📑

Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or want to improve their skills in the field.

However, Verilog and FPGA are very special fields, so it is very difficult to find a lecture that explains them in detail. FPGA manufacturers provide documentation, but there are so many documents in English that it is difficult to know which document to look at.

I have been working as a developer in the industry for over 20 years and currently run a one-man business. I created this course because I wanted to share the knowledge I have accumulated so far with people who are working as developers or preparing to become developers.

The course consists of a total of 4 parts.

This lecture is the third lecture and covers DDR Controller for processing video data. To process video data, a Frame Buffer is required. DDR is fast and cheap, so it is widely used as a Frame Buffer.

This lecture implements a DDR Controller using MIG (Memory Interface Generator) provided by Xilinx. It also implements a Frame Buffer for image data processing. If you understand the contents of this lecture, you can implement any application that uses DDR.

If there is anything you do not understand in the lecture, please post a question through the Inflearn community or the cafe I run and I will answer it.

💾 Please check before taking the class!

This lecture is a text lecture in electronic document format . All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.
The tool used in this lecture is vivado 2018.3.
The board used for the practical training of this lecture is HIL-A35T, which we developed for the lecture. You can purchase it from our company's smart store (Smart Store Link: https://smartstore.naver.com/ihil)
Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.

Lecture Features ✨

Everything about DDR Controller

There are few documents that cover DDR Memory Controller. This lecture explains all the processes in detail. It explains all the processes from creating and simulating Memory IP to implementing DDR Memory Controller for general use and implementing Frame Buffer for image data processing. In addition, each source code is configured so that you can verify it through simulation and understand its operation.

Upgrade your Verilog skills

For those who want to learn Verilog, DDR Memory Controller is a very good skill. There are many people who have a lot of development experience but have not encountered DDR Memory Controller. We provide an opportunity to upgrade Verilog to the next level.

Provides source code applicable to practical use.

For those who purchase this course, we will provide all the sources explained in the course. The sources provided are composed of materials that have been coded and verified from the beginning while producing the course. In addition, they are composed of codes that can be used immediately in the field. We hope that you will become a master of DDR Controller through this course.

📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.

Arty A7-35T board
- Verilog FPGA Program 1 (Arty A7-35T)
- Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)
- Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)
- Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)
- Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)
Zynq mini 7020 board
- Verilog FPGA Program 1 (Zynq mini 7020)
- Verilog ZYNQ Program1 (Zynq mini 7020)
HIL-A35T board (developed in-house for lectures)
- Verilog FPGA Program 1 (HIL-A35T)
- Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)
- Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
- Verilog FPGA Program 4 (MCU Porting, HIL-A35T)

Detailed Curriculum 📚

Section 1. HW Configuration

Section 2. Creating DDR Controller IP

Generate DDR Controller IP using MIG. DDR Controller has many options during the generation process. You need to know and set these options well to generate IP that works properly.
This lecture explains these processes in detail.

Section 3. Simulation

It is very important to understand the behavior of the generated IP.
Understand IP operation through simulation.

Section 4. Implementing User Interface Logic

Based on understanding the behavior through simulation, we implement User Interface Logic that can be used universally.
Implement DDR full-range write, read, and verification and check the results on the board.

Section 5. Improving DDR Memory Access Speed

Added in v2.4, implements a method to improve DDR Memory Access speed.

Section 6. Implementing the Frame Buffer

Implement a Frame Buffer that processes video data using User Interface Logic.

Section 7. Implementing the 32Bits Interface

Added in v2.5, it implements a 32-bit interface using two 16-bit DDR memories.

Section 8. Spartan6 DDR Controller Implementation

Implementing Spartan6 DDR Controller using ISE version 14.7.

Section 9. DDR4 Controller Implementation

Added in v2.7, implements DDR4 Controller.

Recommended for
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Who is this course right for?

Image data processing using FPGA
Frame Buffer Implementation
If you want to learn Verilog
If you want to learn FPGA

Need to know before starting?

Verilog
alive
FPGA

Hello
This is

1,731

Learners

Reviews

127

Answers

4.8

Rating

Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

Verilog HDL을 이용한 FPGA 설계
- CCTV용 ISP ASIC 개발 (약 10년)
- OLED Display 검사장비 개발 (약 3년)
- FPGA를 이용한 장비 개발
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Program
- Visual Studio MFC, C++

입니다.

Curriculum

All

277 lectures

Course Materials:

Lecture resources

Section 1. Table of Contents and Overview

7 lectures

Section 2. HW Configuration

6 lectures

8. HW Configuration - 0
9. HW Configuration - 1
10. HW Configuration - 2
11. HW Configuration - 3
12. HW Configuration - 4
13. HW Configuration - 5

Section 3. DDR Controller IP Generation

23 lectures

Section 4. DDR Controller Simulation

11 lectures

Section 5. Implementing User Interface Logic

45 lectures

Section 6. DDR3 Memory Access Speed

13 lectures

Section 7. Frame Buffer Implementation

32 lectures

Section 8. 32Bits Interface Implementation

32 lectures

Section 9. Spartan6 DDR Controller Implementation

83 lectures

Section 11. Other

3 lectures

Published:

Last updated:

Reviews

All

3 reviews

4.0

3 reviews

anthony734870
Reviews 1
∙
Average Rating 5.0
5
64% enrolled
The explanation is detailed, so it's good to follow along and try it out.
- ihil
  Instructor
  Thank you for your course review~!!
tonyahn9930
Reviews 2
∙
Average Rating 5.0
5
5% enrolled
I just registered. I'm excited. Where can I get the code for the textbook?
- ihil
  Instructor
  Hello. Lecture - Section 0 - Material Sharing Link - If you download the lecture materials, you can find the link to download the materials. I hope this lecture is helpful. Thank you ~!!
achieve123455556
Reviews 4
∙
Average Rating 3.8
2
60% enrolled
Is it because my level is still low? The content feels like it's missing a lot here and there rather than a bridge that's connected.
- ihil
  Instructor
  The content may be a bit difficult. ㅠ This is implemented with code that has been verified on the board. Please study it repeatedly and understand the operation with the program code and simulation. It may be unfamiliar and difficult at first, but if you repeat it, you will gradually understand it and learn it that way. Learning FPGA and Verilog is not an easy path. These days, there are not many people around me who do FPGA and Verilog. I think it is that difficult. When you want to learn FPGA and Verilog, It is very helpful to have reference materials, codes, and boards. When I look at the codes I programmed in the past, there were many errors, and I think I programmed them too funny. When I received the codes that my previous manager had done, there were many ridiculous codes. There are many cases where thousands of warnings occur and grammatically strange codes are used for years because they operate on the board. I have been doing FW for a long time, and I have also handled circuit design and Windows programs to some extent. I have experienced many codes, not just FPGA and Verilog. The content of this lecture is based on my long experience. I am currently developing fpga and verilog in the field. If you want to learn fpga and verilog, I hope you will study repeatedly, even if it is difficult. Also, I hope you will understand the codes in the data room and make them your own so that you can use them well in the field. Thank you for your honest review ~!!

$84.70

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What you will gain after the course

DDR Memory Controller implemented in FPGA 🛠️

FPGA Design by someone with over 20 years of experience 📑

Lecture Features ✨

Everything about DDR Controller

Upgrade your Verilog skills

Provides source code applicable to practical use.

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📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.

Detailed Curriculum 📚

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Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

What you will gain after the course

DDR Memory Controller implemented in FPGA 🛠️

FPGA Design by someone with over 20 years of experience 📑

Lecture Features ✨

Everything about DDR Controller

Upgrade your Verilog skills

Provides source code applicable to practical use.

📢 The course consists of a total of 4 lectures. This is the 3rd lecture.

📢 The lectures vary depending on the practice board. Please be careful when purchasing the lectures.

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