
Verilog FPGA Program 5 (Serdes)
alex
Implement LVDS (Serdes) in FPGA.
Intermediate
FPGA, verilog


Reviews from Early Learners
5.0
haneuli
I am using it like an encyclopedia. I feel once again how happy it is to have a teacher. Thank you!
5.0
miheungsound
I studied FPGA in advance before this lecture, but it was too difficult. I'm watching it once now, and I think I'll learn it happily if I follow this lecture. I think it's a good lecture. I'll definitely succeed.
5.0
wwe0898
Course completed
Verilog RTL Design
FPGA Design
Were you interested in FPGA?
Then do Verilog! 😁
Verilog, which has a syntax similar to the C language, is a Hardware Description Language (HDL) used for electronic circuits and systems. It is used for various purposes, including circuitry, design, verification, and implementation.
Many developers are interested in implementing FPGAs using Verilog, right? However, it is very difficult to find a course that explains this in detail. Now, you can experience a course compiled by a professional with over 20 years of experience, covering content actually used in development! The course material might feel challenging, but if you read through it 3 or 4 times and practice, it will serve as an excellent guide for growing into an FPGA developer.
This course covers the implementation of FPGAs using Verilog HDL in detail. You will learn the entire process of implementing Verilog code, verifying results through simulation, and finally downloading and verifying the implementation on Xilinx FPGA Artix (Arty a7-35T, HIL-A35T) boards. Additionally, it covers IPs provided by Xilinx (related to clocks and memory). By understanding the content explained in this course and mastering your own coding methods, you will become a skilled developer in FPGA design.
📢 Please be sure to check before taking the course!
How to use the vivado tool
Verilog Coding
Creating a testbench and
performing simulation
Check the results by downloading
them to the board
I have been developing through FPGAs for about 20 years. I also have experience creating and releasing ASICs. However, I still haven't fully understood the world of FPGAs. That is how vast the FPGA world is. You need to know many things, including details about tools, HW components, and Verilog. What I have felt while working so far is that in order to handle Verilog or FPGA well, you must have your own program format (coding rules). This lecture explains this part in detail. I hope you master the contents explained in the lecture and develop them into your own format.
This course is intended for those who have some knowledge of Verilog syntax and understand hardware concepts. Since Verilog HDL is similar to the C language, knowing C will be helpful. Additionally, in this course, the final results will be downloaded to a board (Arty A7, by Digilent) to verify the outcomes. Verilog HDL should not end with just checking results in a simulation. Verilog HDL must be downloaded to an FPGA board to verify its operation. For those taking this course, I recommend watching the content first and then definitely purchasing a practice board to verify the results.
If there are any parts of the lecture you don't understand, please post your questions through the Inflearn community or the cafe I operate, and I will provide answers.
The structure of this course is as follows.
We will explain in detail how each process is carried out using Vivado version 2018.3.
The contents of the practice are as follows.
The first practice topic is the counter. Although simple, the counter is a module that is widely used in practice. We will design the counter, create a test bench to run a simulation to verify if the implemented code works correctly, and finally apply it to the board to check the results through LED on/off.
The second practice topic is SPI communication. SPI was chosen because it is relatively easy to implement among various interfaces and is widely used in practice. First, we will implement the SPI Master, followed by the SPI Slave. Then, we will implement communication between the Master and Slave and verify that it operates correctly on the board.
The third part explains Clock and Memory, which are among the most frequently used and easily accessible IPs provided by Xilinx.
The fourth topic is UART communication. We will implement a UART Controller and proceed with verification through communication with a PC.
The fifth practice topic is I2C communication. While I2C communication may seem simple, implementing it in code is by no means easy. It is two to three times more difficult than SPI. If you can implement an I2C Master and Slave in code, you will be able to implement other interfaces without much difficulty. Before writing the code, we will cover in detail how to set the specifications and how to design the SM (State Machine). The implemented I2C Controller will be verified for operation on the board.
The sixth section is newly added content in v2.1. It covers the implementation of an NRZL (Non-Return Zero Level) Decoder. In particular, it explains in detail how to design and use a FIFO. A FIFO is a very important IP used in many fields. Through this chapter, you can understand the process of designing and implementing a FIFO.
The seventh content was added in v2.3. It implements the FMC (Flexible Memory Controller) Interface. In particular, it includes details on how to resolve Timing Violations that commonly occur when using two or more clocks.
The eighth content is a new addition to v2.4. It involves testing the speed (performance) of the FPGA's internal Block Memory and determining the most appropriate speed.
Q. Who is the target audience for this lecture?
You should have a basic understanding of Verilog syntax (beginner level) and possess fundamental knowledge of hardware.
Q. Is there anything I need to prepare in order to take the course?
The lecture is conducted using a practice board (Arty A7 -35T or 100T, manufactured by Digilent). However, if the board is not ready, you can listen to the lecture first and proceed with the content as explained (coding and simulation), then conduct the practice once the board is available. Additionally, JTAG-HS2 (or HS3) is used for downloading to the board.
Q. Which programming tool is used?
This course is designed for Xilinx FPGAs. The software tool used is Vivado version 2018.3. Instructions for software installation are not included. Please install the software tool (Vivado 2018.3 or later) before taking the course.
I have worked as a developer for over 20 years in both large corporations and SMEs, and I currently run a small business. I have developed ISP (Image Signal Processing) ASICs for CCTV and numerous products using FPGAs, such as OLED inspection equipment and DAQ (Data Acquisition Systems). In addition to FPGA, I have extensive experience in FW development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming.
Who is this course right for?
Those who are interested in FPGA
Those who are interested in Verilog
For those who want to level up their Verilog skills
Those who want to level up their FPGA skills
Need to know before starting?
Verilog HDL
FPGA
Career Verified
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4.8
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Courses
I have worked as a developer at both large corporations and SMEs for the past 20 years,
I am currently the CEO of a small company.
Key career highlights include
FPGA design using Verilog HDL
ISP ASIC development for CCTV (approx. 10 years)
OLED Display inspection equipment development (approx. 3 years)
Equipment development using FPGA
MCU FW
STM32
PIC32
AVR, ATMEGA
DSP (TI)
Windows Application Development
Visual Studio MFC, C++
.
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359 lectures
Course Materials:
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16 reviews
5.0
16 reviews
Reviews 2
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Average Rating 5.0
5
I studied FPGA in advance before this lecture, but it was too difficult. I'm watching it once now, and I think I'll learn it happily if I follow this lecture. I think it's a good lecture. I'll definitely succeed.
FPGA is not easy. If you follow the lecture content, your skills will gradually increase. Fighting and I will support you~ Thank you~!!
Reviews 1
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Average Rating 5.0
5
Course completed
Thank you for your hard work~ Congratulations on completing it despite the small amount. I hope you fully understand the lecture content and become a great developer in the field~!! Thank you.
Reviews 2
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Average Rating 5.0
Reviews 4
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Average Rating 5.0
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