Verilog FPGA Program 1

Through this course, students will acquire the basic, core knowledge necessary to learn Verilog.

In this course, students will learn how to implement Verilog using the Zynq board.

This course is a free program that guides you through setting up the AMD Vivado and Python development environments from scratch, as required for FPGA and NPU design projects.

Starting from the operating principles of RISC-V instructions, this is a hands-on CPU design course in which you directly design a 32-bit CPU with a five-stage pipeline, completing the process from Verilog RTL implementation and simulation verification to running it on a physical FPGA. Among the 40 RV32I instructions, 14 instructions essential for learning the core structure of a CPU are selected to progressively build TinyRV32I. You will directly design and verify the key structures that make up a real CPU, including the datapath, pipeline registers, ALU and control circuits, branches, hazards, stalls and flushes, and memory-mapped I/O. The Verilog RTL, testbenches, assembly programs, memory images, and FPGA constraint files used in the course are provided. Ultimately, you will run actual programs on an Arty S7-25 FPGA using the CPU you designed. This course does not end here. After completing the core CPU structure through TinyRV32I, the series continues as a step-by-step CPU design program in which you expand it into a Full RV32I CPU supporting all 40 RV32I instructions in the follow-up course.

You will systematically learn everything from the fundamentals of digital logic circuits to Verilog-HDL syntax, combinational and sequential logic circuit design, and verification through simulation. Drawing on 30 years of experience in Samsung Electronics’ semiconductor division, the instructor will help you clearly understand the relationship between HDL code and actual hardware operation and develop the ability to write synthesizable RTL code.

When you decide to build a CPU, you usually start by looking for a circuit diagram. But the moment you unfold the schematic, questions arise that you cannot answer. Why does this block need to be here? Why are there two ports for reading registers? The answer lies entirely in the instructions. Once you know what the instructions require, the circuits you need are determined. It does not work the other way around. There are already many RISC-V courses. But most of them display values on slides, say "This is how it works," and move on. Students have no way to verify whether those values are correct. This course comes with a Python instruction-execution simulator. Type run ADD, and the machine code is assembled on the spot, the 32 bits are broken down by field, and how the registers change appears on the screen. Every number in the textbook is the result of running this tool, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators are difficult to install. This tool only requires Python. No board, license, or installation is needed. You will execute all 40 RV32I instructions yourself without leaving out a single one, discovering along the way what the circuit needs to do.

This lecture implements a DDR Memory Arbiter.

UART is the most basic and widely utilized serial communication method, making it a very suitable learning topic for beginners new to FPGA design. In this course, we will thoroughly understand the communication principles and frame structure of UART, and based on this, we will proceed with directly implementing transmit/receive logic through RTL (Register Transfer Level) design. By implementing UART on an FPGA, you can systematically develop your digital circuit design skills and gain experience verifying its operation at the actual hardware level through simulation and verification. Furthermore, by learning the method utilizing the MicroBlaze soft processor and Xilinx UART IP, you will gain a broad understanding of processor-based system design flow and interface configuration. This will enable you to acquire comprehensive development capabilities encompassing both logic design and processor design.

As you study CPUs and RISC-V, you may understand what the instructions do but still find yourself asking, “How are these instructions actually executed in hardware?” and “How can I verify that a CPU I designed myself really works correctly?” Many existing resources stop at ISA explanations or simple CPU examples, and many others rely on completed IP, making it difficult to experience the entire process of designing and verifying a CPU yourself and running programs on an actual FPGA. I have spent many years working in R&D and business in the system semiconductor field, and I have observed this learning gap firsthand while teaching semiconductor design and FPGA at a university. For this reason, rather than providing a completed CPU and simply checking that it operates, this course is structured around designing the CPU directly in a White Box approach, starting with the question, “What hardware is required to execute RV32I instructions?” In Volume 3, we expand Volume 2’s TinyRV32I into a Full-Version 32-bit CPU that uses 40 RV32I instructions. We extend the datapath, Decoder, Branch·Jump, and Byte/Halfword Memory Access, and implement Forwarding and Load-Use Interlock so that the 5-stage Pipeline can handle data dependencies on its own. We then integrate CSR, Exception, Interrupt, Trap, and MRET to complete a CPU capable of handling not only normal program execution but also exceptions and external events. The design does not end with RTL Simulation. You will run actual programs on the CPU, compare the results with the Spike Reference Model, and learn the purpose of the RISC-V Architecture Compatibility Test as well as how to perform and evaluate it through real verification cases. Finally, you will implement the verified CPU on an Arty S7-25 FPGA, receive input from Switches and Buttons, run programs, and confirm the results by displaying them on LEDs. The problem this course aims to solve is not simply learning more RISC-V instructions. Its goal is to connect instructions → CPU architecture → Verilog RTL → Pipeline control → program execution → standards-based verification → actual FPGA operation into a single flow, enabling students to fundamentally understand the internal structure of a CPU and develop the engineering skills to design and verify one themselves.

This lecture implements a DDR Memory Arbiter.

ASIC에 대한 전반적인 FLOW를 온라인으로 익히고, 한국반도체아카데미 등에서 진행하는 오프라인 교육을 통하여 전체 프로젝트 진행 및 포트폴리오를 만드는 것을 추천합니다.

If Season 1 was about checking your skills and solidifying the basics, Season 2 is intensive practical training focused solely on 'passing and career transitions.' Beyond simple syntax or gate-level design, you will directly design top-tier, high-difficulty modules (CDC, Synchronous/Asynchronous FIFO, AMBA APB, SPI, I2C, FIR filters, etc.) that frequently appear in coding tests and actual workflows at major corporations and foreign companies. Do you need solid design capabilities that won't waver even under a recruiter's relentless follow-up questions? This course contains all the practical know-how and ultimate coding test problems from ETA, who successfully moved from a regional university to a global semiconductor firm. In this final season, complete your career transition free pass.