When I was working on MCU, I didn't have much trouble with RAM (because there are abundant resources these days). However, as I was studying HW while working on FPGA or Zynq, I started to worry about RAM and had a lot of difficulties. This lecture was a great help. Please continue to provide good lecture materials~!

neulha

Through this lecture, you will be able to implement a DDR controller using FPGA.

ihil

Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

Thank you for your course review. The MCU environment and the FPGA development environment seem to be very different. Maybe they are different worlds. Thank you for helping me with the course. I hope you become a happy and capable developer. Thank you ~!!

verilog

베릴로그

fpga

alex

입문

초급

중급이상

필드 프로그래머블 게이트 어레이

FPGA

outline

HW configuration

Generate DDR Controller IP

Simulation

Implementing User Interface Logic

DDR3 Memory Access Speed

Frame Buffer Implementation

Implementing 32Bits Interface

Spartan6 DDR Controller Implementation

DDR4 Controller 구현