Hardware

Semiconductor

Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)

Name: Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)
Price: 82500 KRW

This course is an advanced course in Microblaze. Through this course, you will learn how to apply Microblaze.

(5.0) 2 reviews

38 learners

ihil

텍스트 강의

fpga

MicroBlaze

verilog

FPGA

What you will learn!

Using MicroBlaze on FPGAs
Verilog program
w5500 interface implementation

FPGA MicroBlaze is a daunting task to study!
You can get a lot of bangs with this lecture 💪

📢 Please note before taking the class.

This course is a text lecture in electronic document (PDF) format. All source files explained in the course are provided to those who take the course. The course source code can be downloaded from Section 0 [Material Sharing Link].
This lecture is a follow-up to the [FPGA MicroBlaze Implementation] lecture. Program installation details are detailed in the previous lecture.

Lecture Topic 📖

This lecture is about MicroBlaze applications . The MicroBlaze basics course focuses on understanding and utilizing the basics of MicroBlaze . The application course explains how to implement high-speed TCP/IP using w5500 based on utilizing block memory . It covers implementing the interface between user logic and MicroBlaze and utilizing it .

This course uses vivado 2022.1 . Installation details are detailed in the Microblaze Basics . This course is based on source code implemented and verified on the Arty A7 board by a developer with over 20 years of development experience. If you fully understand and internalize the content explained in the course, you can become a very capable developer. The source code downloaded from the resource room is advanced code that can be used in practice without any problems . I hope that many people will find it useful in the field .

I recommend this to these people.

1️⃣

Understand Verilog grammar,
Someone with FPGA design experience

2️⃣

Embedded System (FW)
Someone with development experience

What you'll learn 📚

Implementing Vivado Design Block

User logic design and simulation

Vitis application SW implementation

Download the board and check the results

Are you curious about the detailed curriculum?

Overview (3)
Block Memory Interface - 1 (4)
1. Create a project (5)
2. Block Design (7)
3. Add Constraints file (17)
4. Application SW Implementation (12)
5. Check results (24)
  1. Build Project (24)
  2. Program Download (25)
Block Memory Interface - 2 (29)
1. Create a project (30)
2. Block Design (31)
3. User Logic Design (40)
4. Application SW Implementation (50)
5. Download and check results (53)
6. Fix link script (56)
w5500 interface implementation (58)
1. System Block (59)
2. Create a project (61)
3. Block Design (62)
4. User Logic Design (70)
5. w5500 spi timing (74)
6. Source Code Analysis (75)
  1. ax_reg module (75)
  2. eth_task module (77)
  3. eth_task simulation (87)
  4. bramW5500Top module (95)
  5. xdc file (98)
7. Application SW Implementation (99)
  1. data_type.h (105)
  2. ax_common.h (105)
  3. w5500.c, w5500.h (105)
  4. w5500_task.c, w5500_task.h (106)
  5. w5500_socket.c, w5500_socket.h (106)
  6. w5500_loopback.c, w5500_loopback.h (107)
  7. helloworld.c (109)
8. Check Results (110)
  1. Build Project (110)
  2. PC Network Settings (111)
  3. Program Download (112)
  4. Check Results (115)
  5. Download programs to external Flash (118)
9. Conclusion (119)
References (120)
Revision History (121)

Expected Questions Q&A 💬

Q. Who is the target audience for this lecture?

This course is designed for those who understand Verilog syntax, have experience with FPGA design, and have experience developing embedded systems (FW). If you are new to Microblaze, we recommend taking the introductory course before taking this course.

Q. Is there anything I need to prepare to attend the lecture?

This lecture will be conducted on the Arty A7-35T (100T, Digilent) training board. If you don't have a board, please review the content first and then purchase one later to be sure to test it on your board.

Q. What program tools do you use?

We're using the latest version, vitis 2022.1. The installation process is detailed in the Microblaze Basics course.

Introducing the Knowledge Sharer ✒️

History

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming.

Recommended for
these people

Who is this course right for?

Anyone interested in MicroBlaze
Anyone interested in FPGA
Anyone interested in Verilog
For those who want to learn advanced Verilog techniques

Need to know before starting?

C language
Verilog HDL
Xilinx FPGA

Hello
This is

1,647

Learners

Reviews

123

Answers

4.8

Rating

Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

Verilog HDL을 이용한 FPGA 설계
- CCTV용 ISP ASIC 개발 (약 10년)
- OLED Display 검사장비 개발 (약 3년)
- FPGA를 이용한 장비 개발
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Program
- Visual Studio MFC, C++

입니다.

Curriculum

All

121 lectures

Course Materials:

Lecture resources

Section 1. outline

2 lectures

1. outline
2. Data sharing link

Section 2. Block Memory Interface1

25 lectures

Section 3. Block Memory Interface2

29 lectures

28. Block Memory Interface2 - 0
29. Block Memory Interface2 - 1
30. Block Memory Interface2 - 2
31. Block Memory Interface2 - 3
32. Block Memory Interface2 - 4
33. Block Memory Interface2 - 5
34. Block Memory Interface2 - 6
35. Block Memory Interface2 - 7
36. Block Memory Interface2 - 8
37. Block Memory Interface2 - 9
38. Block Memory Interface2 - 10
39. Block Memory Interface2 - 11
40. Block Memory Interface2 - 12
41. Block Memory Interface2 - 13
42. Block Memory Interface2 - 14
43. Block Memory Interface2 - 15
44. Block Memory Interface2 - 16
45. Block Memory Interface2 - 17
46. Block Memory Interface2 - 18
47. Block Memory Interface2 - 19
48. Block Memory Interface2 - 20
49. Block Memory Interface2 - 21
50. Block Memory Interface2 - 22
51. Block Memory Interface2 - 23
52. Block Memory Interface2 - 24
53. Block Memory Interface2 - 25
54. Block Memory Interface2 - 26
55. Block Memory Interface2 - 27
56. Block Memory Interface2 - 28

Section 4. w5500 interface implementation

62 lectures

Section 5. etc

3 lectures

Published:

Last updated:

Reviews

All

2 reviews

5.0

2 reviews

jblee38036
Reviews 2
∙
Average Rating 5.0
5
100% enrolled
This is helpful information for practical use.
- ihil
  Instructor
  Thank you for your course review~!!
neulha
Reviews 12
∙
Average Rating 5.0
5
100% enrolled
I started FPGA late ㅠㅠ Thank you for opening this kind of information like Danbi! I'm really happy that the feeling of being lost has been resolved since I started studying from scratch~
- ihil
  Instructor
  Thank you for your course review. I remember feeling lost when I first encountered FPGA and Verilog. I understood the theory, but I think I realized little by little what it actually meant while working. I am grateful that the course helped you, and I hope you become a great developer. Thank you ~!!

$63.80

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What you will learn!

Lecture Topic 📖

I recommend this to these people.

What you'll learn 📚

Expected Questions Q&A 💬

Introducing the Knowledge Sharer ✒️

History

Recommended for these people

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Curriculum

Reviews

ihil's other courses

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