
STM32 CAN通信
ihil
STM32 MCUを使用してCAN通信を実装する方法を説明するテキスト形式のレッスンです。
초급
CAN, MCU
This is a lecture on designing FPGA programs using Verilog HDL.
Verilog RTL Design
FPGA Design
simulation verification
Validate on the target board
Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or want to improve their skills in the field.
However, Verilog and FPGA are very special fields, so it is very difficult to find a lecture that explains them in detail. FPGA manufacturers provide documentation, but there are so many documents in English that it is difficult to know which document to look at.
I have been working as a developer in the industry for over 20 years and currently run a one-man business. I created this course because I wanted to share the knowledge I have accumulated so far with people who are working as developers or preparing to become developers.
The lecture consists of a total of 4 parts.
This lecture is the first and most important lecture. It is designed so that even beginners can easily follow along, by explaining how to use the tool, explaining the code, simulating the code, and checking the results on the development board.
Becoming a capable developer is not an easy task. It requires a lot of effort. It is very good to have a friendly guide during that difficult process.
I hope you use this lecture as your own reference. I hope you make the contents of this lecture almost by heart. A good developer is not something you can learn by sight. You have to repeat the process of coding yourself, checking it with simulation, and verifying that it works as you want on the board countless times.
This course contains a lot of content. If you are not an experienced developer, it may be difficult to understand everything at once. You will be able to gradually make it your own by repeatedly coding, simulating, and checking the results on the board.
If you can fully understand and utilize the contents of this lecture, you can become a very good developer.
If there is anything you do not understand in the lecture, please post a question through the Inflearn community or the cafe I run and I will answer it.
This lecture is a text lecture in electronic document format . All source files explained in the lecture will be provided to those who take the lecture. The lecture will be produced as a video in the future.
The tool used in this lecture is vivado 2018.3.
The board used for the practical training of this lecture is HIL-A35T, which we developed for the lecture. You can purchase it from our company's smart store (Smart store link: https://smartstore.naver.com/ihil)
Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachments'.
Lecture 1: Verilog FPGA Program 1
Implementing basic functions
Lecture 2: Verilog FPGA Program 2
Microblaze
Lecture 3: Verilog FPGA Program 3
DDR Controller
Lecture 4: Verilog FPGA Program 4
MCU Porting
Basics: Basics of FPGA Utilization Using Verilog
Arty A7-35T board
Verilog FPGA Program 1 (Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)
Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)
Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)
Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)
Zynq mini 7020 board
Verilog FPGA Program 1 (Zynq mini 7020)
Verilog ZYNQ Program1 (Zynq mini 7020)
HIL-A35T board (developed in-house for lectures)
Verilog FPGA Program 1 (HIL-A35T)
Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)
Verilog FPGA Program 3 (DDR Controller, HIL-A35T)
Verilog FPGA Program 4 (MCU Porting, HIL-A35T)
How to use Vivado tools
Verilog coding
Create a tech bench and run a simulation
Download the results to the board and check them
Section 1. HW Configuration
Section 2. LED Control Using Counter
Control an LED using the most basic counter. Understand the entire process of creating a project, adding code, generating a Bitstream, and downloading it to the board to see the results.
Section 3. Simulation
Understand the simulation process for verifying code.
Section 4. SPI Master Implementation
Implement SPI Master. Define the specifications and implement the code.
Implements a very important State Machine (SM) in Verilog.
Section 5. SPI Slave Implementation
Implements a SPI Slave.
Section 6. Implementing SPI Communication
Implement communication between SPI Master/Slave and check the results on the board.
Section 7. Xilinx IP
Xilinx provides many IPs. Among them, I will explain the most commonly used Clock and Memory related IPs.
Section 8. Uart Controller Implementation
Implement Uart Tx, Rx Controller and implement Loopback communication with PC.
Section 9. I2C Controller Implementation
We implement an I2C Controller, which is one of the most difficult serial communications.
Section 10. NRZLDecoder implementation
NRZL is one of the line coding methods for digital transmission.
Added as an application.
Section 11. Implementing the FMC Interface
Implements the FMC (Flexible Memory Controller) Interface.
Contains information on how to resolve Timing Violations that frequently occur when using two clocks.
Section 12. Block Memory Speed
Test the speed (performance) of Block Memory inside the FPGA.
Block Memory explains optimal speed.
Who is this course right for?
If you are interested in FPGA
Anyone interested in Verilog
If you want to upgrade your Verilog skills
If you want to upgrade your FPGA
Need to know before starting?
Verilog HDL
FPGA
1,647
Learners
66
Reviews
123
Answers
4.8
Rating
19
Courses
저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고
현재는 작은 기업의 대표로 있습니다.
주요 경력사항은
Verilog HDL을 이용한 FPGA 설계
CCTV용 ISP ASIC 개발 (약 10년)
OLED Display 검사장비 개발 (약 3년)
FPGA를 이용한 장비 개발
MCU FW
STM32
PIC32
AVR, ATMEGA
DSP (TI)
Windows Application Program
Visual Studio MFC, C++
입니다.
All
366 lectures
Course Materials:
$84.70
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