Verilog FPGA Program 1 (Zynq mini 7020)

Name: Verilog FPGA Program 1 (Zynq mini 7020)
Price: 110000 KRW
Rating: 5 (3 reviews)

In this course, students will learn how to implement Verilog using the Zynq board.

(5.0) 3 reviews

82 learners

alex

텍스트 강의

베릴로그

verilog

하드웨어

zynq

Verilog HDL

FPGA

Reviews from Early Learners

What you will gain after the course

Verilog coding
Utilizing ZYNQ Board
How to use Vivado, Vitis
Create a Test Bench and Verify Simulation
Download to board and check results

The core of implementing and practicing using the Zynq board.

📢 Please note before taking the class.

This course is a text lecture in electronic document (PDF) format (approximately 110,000 characters). All source files covered in the course are provided to those who take the course. The course source code can be downloaded from Section 0 [Material Sharing Link].

Verilog implementation using the Zynq board

✅ Code implementation ✅ Simulation verification using Text Bench ✅ Board verification

Before coding, we analyze the overall system and provide know-how on how to code efficiently. We provide easy-to-understand explanations based on extensive techniques and know-how gained from over 20 years of field experience. Furthermore, the source code included in the lectures is not for study purposes but rather is used in real-world applications. All attendees will receive access to the full source code used in the lectures.

The first half of the lecture will cover the following two topics:

Install Vivado 2022.1
Download the code implemented on the Zynq board and check the results.

In the latter part of the lecture , we will verify the results downloaded to the board through coding and simulation verification for each topic.

LED control using counter
SPI Controller Implementation
UART Controller Implementation
I2C Controller Implementation
Uses Xilinx IP (Clock Generator, Memory Generator)
NRZL Decoder implementation
Implementation of FMC (Flexible Memory Controller) Interface

_{FPGA Utilization with Verilog for ZYNQ - Lecture Preview}

Detailed Curriculum

outline
HW configuration
SW installation
Download the ZynQ board
1. Basic Template Configuration
  1. Create a project
  2. Create Block Design
2. Download in Debug Mode
  1. Add source code
  2. Bitstream generation
  3. Run and download Vitis
3. Download using FSBL (First Stage Bootloader)
  1. Create an FSBL project
  2. Create Boot Image
  3. Download the board and check the results
4. Download using FSBL, Application SW
  1. Create an FSBL project
  2. Create an Application Project
  3. Create Boot Image
5. Download the board and check the results
  1. LED control using counter
  2. Create a project
  3. Project screen configuration
  4. Add source code
  5. Text Editor Settings
  6. Code implementation
  7. XDC implementation
  8. Generate Bitstream
  9. Check results
6. Simulation
  1. Add simulation source file
  2. Implementing the tb_led_counter.v code
  3. Simulation in progress
  4. Simulation results
7. About the code
  1. Implementable code, non-implementable code
  2. The basic unit of code is Clock.
  3. All code is processed in parallel.
  4. ternary operator
  5. Use Register
  6. FSM (Finite State Machine)
8. Spi Master implementation
  1. Specs
  2. Code implementation
    1. Port definition
    2. State definition
    3. Code implementation
    4. Timing diagram
  3. Simulation
    1. Test bench implementation
    2. Check simulation results
9. Spi Slave Implementation
  1. Specs
  2. Code implementation
    1. Port definition
    2. State definition
    3. Code implementation
  3. Simulation
    1. Test bench implementation
    2. Check simulation results
10. Spi communication implementation
  1. Button noise removal
    1. Button circuit
    2. Code implementation
    3. Simulation
  2. SPI Task Implementation
    1. Port definition
    2. Button noise removal
    3. State definition
    4. Code implementation
  3. Simulation
    1. Test bench implementation
    2. Check simulation results
  4. Implementing the UsetTop module
  5. Add xdc file
  6. Generate Bitstream
  7. Download the board and check the results
11. Use of Xilinx IP
  1. Create a Clock
  2. Memory creation
    1. Block Memory Generator
  3. Memory Test
    1. Single Port RAM
    2. Simple Dual Port RAM
    3. Other memory
12. UART Controller Implementation
  1. Uart Tx implementation
    1. Code implementation
    2. simulation
  2. Uart Rx implementation
    1. Create FIFO
    2. Code implementation
    3. simulation
  3. Uart Controller Implementation
  4. LoopBack implementation
    1. composition
    2. Code implementation
    3. simulation
    4. Implementing the UserTop module
    5. xdc creation
    6. Generate Bitstream and XSA files
    7. Check results
13. I2C Controller Implementation
  1. I2C Controller Specifications
    1. Start, Stop Condition
    2. 8-bit data transmission
    3. Slave ID
    4. I2C Write Data Structure
    5. I2C Read Data Structure
  2. I2C Master Implementation
    1. i2c_master write signal analysis
    2. i2c_master read signal analysis
    3. i2c_master code implementation
    4. i2c_master simulation
    5. Check results
    6. i2c_master8x8 implementation
    7. i2c_master8x8 simulation
  3. I2C Slave Implementation
    1. I2C Slave Signal Analysis
    2. i2c_slave8x8 code implementation
    3. i2c_reg8x8 implementation
    4. i2c_slave8x8, i2c_reg8x8 simulation
  4. I2C TASK
    1. i2c_task code implementation
  5. Implementing the UserTop module
  6. Add xdc file
  7. Generate Bitstream and XSA files
  8. Download the board and check the results
14. NRZL Decoder implementation
  1. System Overview
  2. Code implementation
    1. Create a clock
    2. Create FIFO
    3. data_counter implementation
    4. noise_reduction implementation
    5. data_encoder implementation
    6. nrzlDecTop implementation
    7. Implementing the UserTop module
    8. xdc implementation
    9. Create Bitstream and XSA files and check the results
    10. conclusion
15. FMC Interface Implementation
  1. FMC Timing
  2. Code implementation
    1. fmc_model.v
    2. simulation fmc_model
    3. fmc_interface.v
    4. sys_host.v
    5. spram_32x8192
    6. simulation fmc_interface
    7. fmc_top.v
    8. UserTop.v
    9. UserTop.xdc
  3. Bitstream generation
  4. Resolving Timing Errors
  5. Download the board and check the results
  6. conclusion
16. Revision History

Q&A 💬

Q. Who is the target audience for this lecture?

This course is designed for those interested in learning Verilog and FPGAs. This course restructures the "Using FPGAs with Verilog" section to enable implementation on the Zynq board. All source code is verified on the Zynq mini 7020 (7010) board.

Q. Is there anything I need to prepare to attend the lecture?

All of the lecture content can be practiced on the Zynq mini 7020 (7010) board. Having a Zynq mini 7020 (7010) board available will be very helpful, as you can implement the code yourself and verify the results.

Q. What program tools do you use?

I'm using Vivado version 2022.1. The lecture includes instructions on installing tools, so please follow the instructions to install them.

Q. Where can I buy the Zynq mini board?

You can purchase it through domestic shopping malls or AliExpress.

Accumulated with 25 years of experience
We share our know-how on utilizing Verilog.

I've worked as a developer for over 20 years at both large and small companies, and I currently run a small business. I've developed an ISP (Image Signal Processing) ASIC for CCTV, and I've developed numerous FPGA-based products, including OLED inspection equipment and DAQ (Data Acquisition System). Beyond FPGAs, I have extensive experience in software development (STM32, PIC32, AVR, ATMEGA, etc.), circuit design, and Windows programming.

💾 Please check the lecture environment.

The practice environment uses Windows OS and Vivado 2022.1.
This lecture is a text lecture in electronic document (PDF) format (approximately 110,000 characters).

Recommended for
these people

Who is this course right for?

For those who want to learn FPGA
For those who want to learn Verilog
For those who want to learn Zynq

Need to know before starting?

C language
Verilog Language (Basics)

Hello
This is

1,731

Learners

Reviews

127

Answers

4.8

Rating

Courses

저는 지난 20여년 동안 대기업, 중소기업에서 개발자로 일해왔고

현재는 작은 기업의 대표로 있습니다.

주요 경력사항은

Verilog HDL을 이용한 FPGA 설계
- CCTV용 ISP ASIC 개발 (약 10년)
- OLED Display 검사장비 개발 (약 3년)
- FPGA를 이용한 장비 개발
MCU FW
- STM32
- PIC32
- AVR, ATMEGA
- DSP (TI)
Windows Application Program
- Visual Studio MFC, C++

입니다.

Curriculum

All

381 lectures

Course Materials:

Lecture resources

Section 1. outline

8 lectures

Section 2. HW configuration

2 lectures

Section 3. SW Installation

5 lectures

11. SW Installation - 0
12. SW Installation - 1
13. SW Installation - 2
14. SW Installation - 3
15. SW Installation - 4

Section 4. Download ZynQ Board

54 lectures

Section 6. Simulation

9 lectures

Section 7. About the code

4 lectures

Section 8. SPI Master

16 lectures

Section 9. SPI Slave

12 lectures

Section 10. SPI communication

17 lectures

Section 11. Using Xilinx IP

42 lectures

Section 12. UART Controller Implementation

36 lectures

Section 13. I2C Controller Implementation

66 lectures

Section 14. NRZL Decoder Implementation

40 lectures

Section 15. FMC Interface Implementation

48 lectures

Section 16. etc

2 lectures

Published:

Last updated:

Reviews

All

3 reviews

5.0

3 reviews

ghddrms14061304
Reviews 1
∙
Average Rating 5.0
5
10% enrolled
Hello, I'm a student who recently purchased your course. I'm writing because I'm not sure how to utilize the course materials. Is my coding skills improving by just typing in the source code and questioning why it was coded that way? I would be very grateful if you could provide me with a specific learning method.
- ihil
  Instructor
  Hello, Learning Verilog and FPGA is very different from learning higher-level languages (C, App, Java, etc.). Verilog and FPGA are closely related to hardware. It's about designing the hardware itself. For example, if you think about UART communication, in the upper Application layer, you create a serial protocol and implement communication. In the FPGA layer, you design and implement the UART Controller itself. What is implemented in the FPGA layer is implemented in Main Clock units. It's about implementing how signals are implemented for each clock. In the Application, you implement code at the Protocol level. To study Verilog and FPGA, it may not be very meaningful to do it simply for study purposes. The best way is to learn basic functions (you need to learn to implement code as you like and use tools) and implement something new while doing real projects. You can think of this lecture as learning the prerequisite technologies for proceeding with real projects. To do a real project, it is very important to handle Verilog, FPGA, tools, etc. freely. You need to familiarize yourself with the process of coding with Verilog, verifying with simulation (if there is an error, modify the code and verify with simulation again), and checking the operation by uploading the implemented content to the board. If you are somewhat familiar with the contents of this lecture, you can proceed with projects from small things in actual practice. A recent project I worked on was implementing a Frame Converter (DDR3) in an FPGA to output image data coming from a PC via USB to LVDS. To implement these things, you need the contents of this lecture, implement DDR3 Controller, and understand LVDS. Anyway, learning Verilog and FPGA is not easy. However, I believe that if you learn the basic functions well and acquire various technologies while working on projects in the field, you will become a good developer. Please learn with patience. Thank you.
- ghddrms14061304
  First of all, thank you so much for the detailed reply. As I take the lectures, if I have any questions or get stuck, would it be okay to ask questions here? If there is a more convenient way to contact you, such as by email, please let me know.
- ihil
  Instructor
  You can send it via email or post your question on the cafe I run. Email: alex@ihil.co.kr Cafe: Cafe.naver.com/worshippt Thank you.
- ghddrms14061304
  Okay, I understand. Have a great day today. Thank you.
hyp6636
Reviews 5
∙
Average Rating 5.0
5
75% enrolled
It's harder than I thought to find an FPGA design lecture, but this is a fun lecture that I can follow along step by step while looking at the textbook!!! In addition to this lecture, please make many, many other lectures that utilize the Zynq board~!! I want to upgrade my skills by taking all of them, gaining experience, and practicing. Thank you~!
- ihil
  Instructor
  Thank you for your review. I worked hard to make it, so this kind of review is a great help. Verilog and FPGA are not easy to learn. However, if you learn step by step, your skills will gradually improve and you will gain confidence. I hope you will become a capable developer through the lecture. Thank you ~!!
hotak3210195
Reviews 5
∙
Average Rating 5.0
5
100% enrolled
It helped me with my coding style.
- ihil
  Instructor
  Thank you for helping me with my coding style. I think it is very important for developers to develop their own coding style. I think that using SM(State Machine) in algorithm development is very important and useful as time goes by. I recommend you to use SM a lot. Thank you ~!!

$84.70

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Reviews from Early Learners

What you will gain after the course

Verilog implementation using the Zynq board

Q&A 💬

Accumulated with 25 years of experience We share our know-how on utilizing Verilog.

Recommended for these people

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Curriculum

Reviews

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Accumulated with 25 years of experience
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Hello
This is