Basic UVM Testbench (Circuit Design Verification)
MetaEncore
Through this course, you will understand the UVM Class library and learn testbench design techniques using UVM.
Basic
Verilog HDL, system-verilog, uvm
단순 문법 강의가 아닙니다.
Synopsys와 DUT로 구현된
현업 검증팀의 워크플로우를 그대로 담았습니다.
It was a beneficial lecture where I could learn about System Verilog.
It was really great to be able to learn SystemVerilog in such detail. I had been looking for an easy and detailed lecture but couldn't find one, then I came across this course. I could get a general understanding of the content from the table of contents, and the explanations about the topics and what would be discussed at the beginning helped me understand better. Also, by introducing an environment where I could run the corresponding code, I was able to run the testbench I wrote. This allowed me to see the results, making it more relatable. Furthermore, there were detailed explanations about the Design for DUT, so I could understand what verification work actually verifies. I've only listened to a little bit of the lecture so far, but I'm really satisfied up to this point.
I think this is a lecture with content that's not easily accessible elsewhere. It was great to have detailed content on topics like test coverage, how to set up actual environments, and what to do if tools aren't available. It was a good lecture that came at just the right time when I was considering switching my career from Verilog design to SystemVerilog verification.
The theory and practice were well-balanced, so I could listen without getting too bored. Personally, the curriculum is clean and detailed to the point where just a little more effort would be enough, so it would be good for complete beginners to approach, and it seems like it would be a satisfying lecture for those who are relearning knowledge as well. I briefly looked at SystemVerilog and became interested in verification, Since it's a hot field and job role recently, I think if you're interested, you should definitely take this course as it will be really helpful in the job market in the future.
I'm learning SystemVerilog for the first time and it's really like a university lecture, which is great!! I've been doing only Verilog so far, but someone suggested I try SystemVerilog this time, so I looked around and ended up taking this course - it's so good! I've tried a few other courses, but they just briefly cover things like interface and class in a light way, but this one covers all the details thoroughly, so if I have questions later, I think it'll be great to look it up in the table of contents and re-watch just that part. It feels more like a real university textbook rather than a cram school lecture?? You cover everything and also highlight the important parts among them, so it seems good for both looking up things I don't know later and immediately applying what I've learned. It's not just listing concepts one after another, but at the beginning you explain the structure and role, so while listening to the concepts, I could guess "ah, this is roughly what it's about" and "this is what this function does," which made it better to listen to. You call it basic, but it doesn't really seem basic 😆😆😆 The examples are explained in detail too, so I was able to write a testbench on my own and run it, and you explained the simulation methods in detail too, which was great, and having the scripts was so good!! Later, if I add other functions or sequences?? BFM??? and run them, and increase coverage, I think I'll graduate from basic 😊😊 I thought you'd immediately give me a design and have me write a testbench, but there were explanations of what the design is, what APB is, what completer is, etc., so I could roughly understand "ah, this is what I need to verify," which was really good. Also, when I had questions during the lecture, you explained in great detail, so thank you! I totally recommend this course!! I'm satisfied 😊😊 I've introduced it to people around me a bit too!!!! Especially for electronics majors who have studied Verilog, even if you don't necessarily do SystemVerilog, I think it would be good for studying Verilog too since there's Verilog code in the practice materials!!
