It was really great to be able to learn SystemVerilog in such detail. I had been looking for an easy and detailed lecture but couldn't find one, then I came across this course. I could get a general understanding of the content from the table of contents, and the explanations about the topics and what would be discussed at the beginning helped me understand better.
Also, by introducing an environment where I could run the corresponding code, I was able to run the testbench I wrote. This allowed me to see the results, making it more relatable.
Furthermore, there were detailed explanations about the Design for DUT, so I could understand what verification work actually verifies.
I've only listened to a little bit of the lecture so far, but I'm really satisfied up to this point.

ysw9411217848

You will learn the basic syntax of SystemVerilog and testbench design techniques using SystemVerilog classes.
Additionally, you can experience and learn the complete basic cycle of hardware circuit design verification by utilizing VCS, an EDA Tool from Synopsys used in the industry.

Related search terms
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Basic SystemVerilog Testbench (Circuit Design Verification)

ysw941121,
Thank you for the course review.
I hope it was helpful for your work.

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회로검증

시스템베릴로그

MetaEncore

Veri-Fun

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

system-verilog

verification

system-verilog-dpi

Course Overview and Environment Description

SystemVerilog Testbench Structure

SystemVerilog Language Basics for Verification

SystemVerilog Class for Verification

Concurrency 와 Inter-thread Communication

Functional Coverage