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Semiconductor

Basic UVM Testbench (Circuit Design Verification)

Through this course, you will understand the UVM Class library and learn testbench design techniques using UVM.

18 learners are taking this course

Level Basic

Course period 6 months

  • MetaEncore
Verilog HDL
Verilog HDL
system-verilog
system-verilog
uvm
uvm
Verilog HDL
Verilog HDL
system-verilog
system-verilog
uvm
uvm

What you will gain after the course

  • SystemVerilog Testbench Basic Concepts

  • Understanding UVM Components and How to Write a Testbench

  • UVM Simulation Technique (Using VCS)


Still finding UVM verification difficult?
[UVM TB] Your confidence changes from the design stage.

Confidently performing complex chip design verification through UVM Testbench design
This is the core competency of a skilled verification engineer.


Are you repeatedly working all-nighters due to project delays caused by RTL design errors?

Have you ever experienced the frustration of a re-spin due to functional verification errors?

Are you missing critical aspects by overlooking the importance of verification in complex SOC design flows?

Through this course, you can build a solid foundation in UVM Testbench design,
and grow into an engineer who can confidently verify even complex chip designs.


From understanding the UVM class library
to practical UVM testbench design techniques,
develop the core competencies to verify complex chip designs.


Beyond simple theoretical learning,
take a leap forward as a verification engineer and
grow into a recognized expert in the field.

After completing this course, you will


You will gain a clear understanding of the core principles of UVM Testbench design.

  • You will gain a deep understanding of the structure of the UVM class library and the role of each element, enabling you to independently build UVM-based testbench design techniques essential for complex chip design verification.
    If you have experience with Verilog HDL or SystemVerilog TB design, the transition to UVM will be even smoother.

Acquire practical skills in building UVM testbenches.

  • Master key UVM concepts including UVM components, transactions, sequences, configuration and factory mechanisms, and TLM communication through hands-on demonstrations and labs. With this foundation and understanding of the entire SOC design flow from RTL design to tape-out, you'll be able to confidently write testbenches that can be immediately applied in real verification environments.

Perform efficient verification in UVM simulation environments.

  • Learn the UVM simulation flow in industry-standard simulator environments such as Synopsys VCS, and experience practical verification processes including component phasing, transaction/sequence utilization, monitor and scoreboard implementation, and functional coverage writing. Through this, you can systematically build the technical stack required as a verification engineer and contribute to increasing project success rates.

Establish a foundation for growth as a verification engineer.

  • You will understand the latest semiconductor design and verification trends and recognize the importance of UVM verification in preventing re-spins due to functional errors. Through this course, you can improve your UVM testbench writing skills to become a verification expert in the SOC/IP design field or strengthen your related job competencies.


✔️

Core Know-how for
Building UVM Verification Environments

UVM-Based Verification,
Strengthening Practical Skills

This course systematically covers everything from understanding the UVM (Universal Verification Methodology) Class Library, which is core to complex semiconductor design verification, to Testbench design techniques. Based on the fundamental concepts of SystemVerilog Testbench, you will learn UVM elements in depth and master UVM simulation techniques using the actual VCS simulator.

Practical UVM Testbench
Design and Simulation

The course covers in detail the core UVM component design methods, including UVM Testbench structure, Phasing mechanism, and Transaction and Sequence utilization. In particular, you can develop practical skills by writing Testbenches directly in the Synopsys VCS simulator environment and practicing message output, Stimulus Generation, Component Configuration, Monitor and Scoreboard implementation.

UVM Verification
Source Code and Materials

All UVM Testbench structure-related source code and example files used in the course are provided. Through these, you can directly run VCS simulations and strengthen your practical skills as a verification engineer by learning UVM's key concepts such as UVM Class Tree, Architecture, Phasing, Transaction, Sequence, Configuration, Factory, and TLM communication through hands-on practice.


📚

UVM-based verification automation,
Start building a solid foundation!

섹션1_소개

Section 1

UVM Overview and Verification Environment Setup

This section introduces the overall content of the UVM testbench course and explains the importance of the SOC design flow. It also covers the latest verification trends and the role of UVM, while clearly defining the course objectives and prerequisites.


섹션2_소개

Section 2

SystemVerilog Object-Oriented Programming Review

Review the object-oriented programming (OOP) concepts of SystemVerilog that form the foundation of UVM. Deepen your understanding of classes, inheritance, polymorphism, interfaces, and static and singleton patterns to build a foundation for UVM component design.


섹션3_소개

Section 3

UVM Testbench Structure and Components

Learn the basic structure of UVM testbenches and the hierarchical structure of the UVM base class library. Understand the roles and operation methods of UVM component classes, and learn how to build actual UVM testbench architectures.


섹션4_소개

Section 4

Understanding UVM Phasing Mechanism

You will learn in-depth about the Phasing mechanism that controls the execution flow of UVM testbenches. You will understand the operating principles of component phases and Phase Objection techniques, and use them to effectively manage test simulations.


섹션5_소개

Section 5

UVM Transaction Modeling and Utilization

Understand the importance of transactions in UVM testbenches and learn how to design and utilize transaction classes. Master the implementation and usage of constraints, parameterized transactions, and transaction methods.


섹션6_소개

Section 6

Stimulus Generation Using UVM Sequence

Learn how to write and execute test sequences using UVM sequence classes. Learn to implement complex test scenarios using Top Sequencer and Top Sequence, and manage sequence libraries.


섹션7_소개

Section 7

UVM Configuration and Factory Mechanisms

Understand the UVM component hierarchy and configuration mechanisms. Learn how to dynamically create and manage components using the UVM Factory, and how to enhance the flexibility and scalability of the testbench through this approach.


섹션8_소개

Section 8

Communication Between UVM Components (TLM)

Learn Transaction Level Modeling (TLM) techniques for effective communication between UVM components. Understand TLM 1.0 and TLM 2.0 standards, and build a verification environment using monitors and scoreboards.


섹션9_소개

Section 9

Writing UVM Scoreboard and Functional Coverage

Design a UVM scoreboard to verify DUT behavior and define functional coverage to ensure verification completeness. Learn the role of monitors within agents and coverage measurement methods.


We can solve these concerns!


📌

Entry-level Semiconductor Verification Engineers

Those who have built verification environments based on Verilog but are now in a situation where they need to adopt SystemVerilog and UVM due to increasingly complex designs

📌

Experienced Verification Engineer

Those with experience writing Verilog Testbenches who want to systematically learn the UVM methodology to improve reusability and productivity, and keep up with the latest verification trends

📌

SystemVerilog Designer

Those who need to write testbenches to verify the functionality and performance of designed RTL code, but feel overwhelmed by UVM's level of abstraction and object-oriented concepts

Notes Before Enrollment


Lab Environment

  • Operating System: Linux (Ubuntu or similar recommended)

  • Simulator: Synopsys VCS (used in the course)

  • PC Specifications: 8GB RAM or more, 50GB or more disk space recommended

Prerequisites and Important Notes

  • Understanding of basic SystemVerilog syntax and classes is required.

  • Experience with Object-Oriented Programming (OOP) will be very helpful for learning.

  • Familiarity with the Linux command-line environment is recommended.

  • Experience with simulators will be even more effective.

Learning Materials

  • PDF materials for the labs conducted in the course will be provided.

  • Lab example code and UVM library are provided.

  • A VCS simulation environment setup guide is included.


Recommended for
these people

Who is this course right for?

  • People who are starting verification and want to try using UVM

  • For those who want to transition from Verilog TB to SV, UVM TB

Need to know before starting?

  • Command processing and scripting in Linux environments

  • Verilog, SystemVerilog design, verification experience

  • Object oriented programming experience - Plus

Hello
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118

Learners

14

Reviews

10

Answers

5.0

Rating

5

Courses

Market demand for application-specific integrated circuits (ASICs) such as AI (Artificial Intelligence) and IoT (Internet of Things) is increasing, and many chips are actually being designed, but it is rare for them to lead to substantial changes in our lives.

This is because many ASIC designs are either functionally flawed or fail to meet the planned performance requirements. To enrich our lives by creating high-quality semiconductors, services that provide advanced functional and performance verification capable of handling increasingly large and complex designs are essential. MetaEncore is a company that aims to increase the number of semiconductors that benefit humanity by providing such services.

Curriculum

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45 lectures ∙ (9hr 43min)

Course Materials:

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$338.80

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