Basic Design Synthesis Training (Digital Circuit Design Implementation)

Synthesis

What is synthesis?

• Converting a Register Transfer Level design written in an HDL such as Verilog into a Gate Level design.

• During the conversion process, the design is optimized according to constraints known as Synopsys Design Constraints.

• Finally mapping to standard cells provided by the foundry.

  
  

The beginning of digital circuit design implementation: learning synthesis.

The beginning of the digital circuit design implementation stage; the chip is only complete when you understand it properly.

Synthesis is the first gateway connecting the abstract and physical stages.
Ultimately, understanding synthesis means understanding the overall circuit design process.
In the industry, companies prefer new employees with experience in synthesis and timing verification.
However, because the related tools are expensive and inaccessible, it is a difficult field to study in school or through self-teaching.
In this course, you can experience the Design Compiler-based synthesis process used in the industry step-by-step,
and it explains many concepts used in circuit implementation roles beyond just synthesis.

What is covered in the synthesis lecture

• Section 1. Basic Digital Logic Circuit concepts required for synthesis

  • Digital System

  • Timing concepts

• Section 2. Detailed understanding of the Digital Chip Design Flow

  • SoC / ASIC

  • Physical Implementation (Front-End) / Physical Design (Back-End) Flow

• Section 3. Understanding synthesis using Synopsys Design Compiler, the most widely used synthesis tool in the industry

  • Design Setup

  • Synopsys Design Constraints (SDC)

  • Synthesis Techniques

  • Timing Analysis

    
    

What you will gain from the synthesis lecture

• Preparation process required for synthesis

• Understanding SDC commands for design optimization

• Timing Concepts and Analysis

• Various techniques in the compile process

• Understanding of terms used in practice

Requirements

• Since this is the process of mapping Digital Design into "physical" gates, the following prerequisite knowledge is required:

  • Digital Logic Circuits

  • CMOS operating principles

  • Basic knowledge of the Verilog language

• Linux environment

  • While it is not a requirement for the course content, the Linux environment is used across all practical work in the industry.

• TCL for communicating with EDA tools

  • Similarly, it is not mandatory, but it is recommended to study it in your spare time.

    
    

Reference sites for study materials related to the lecture

• TCL, the most widely used scripting language in the PI / PD field

  • https://tcltk.co.kr

Hands-on challenge course in progress

• What if you want to try hands-on practice after taking the lecture?

  • Inflearn Challenge Course [2-Week Synthesis Practice Challenge] is currently running (First 5 people per batch)

    • 3rd Batch Recruitment in Progress: https://inf.run/ePpjr

  • This is a great opportunity to try out Synopsys' Design Compiler.