MetaEncore's Reviews - Inflearn

MetaEncore

@metaencorehr

Students

138

Reviews

18

Course Rating

5.0

Reviews

wwa99819313
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Basic SystemVerilog Testbench (Circuit Design Verification)
Basic SystemVerilog Testbench (Circuit Design Verification)
This was a lecture where I could review the basics of SystemVerilog that I already knew, while also discovering parts I hadn't known before.
laylar00217581
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Basic UVM Testbench (Circuit Design Verification)
Basic UVM Testbench (Circuit Design Verification)
I think I will be able to build a solid foundation in UVM.
somisomisomsomi
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Basic UVM Testbench (Circuit Design Verification)
Basic UVM Testbench (Circuit Design Verification)
I listened to this because I wondered if there would be any overlap with the previous SystemVerilog lecture, and it was great because the content went further and included additional explanations. I think it's a good way to build a foundation in UVM.
onsaemiro1
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Basic Design Synthesis Training (Digital Circuit Design Implementation)
Basic Design Synthesis Training (Digital Circuit Design Implementation)
This course was very helpful in systematically understanding everything from digital logic circuits to the synthesis process. Each section is structured step-by-step, making it easy for beginners to follow the flow, and the clear explanations of concepts frequently encountered in practice made it easy to understand. The explanations of timing analysis and the synthesis process were particularly useful enough to be directly applicable to actual work. The balance between examples and explanations was well-maintained, allowing me to learn complex content without feeling overwhelmed. Thank you for the great course.
dwoo09109047
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Basic Design Synthesis Training (Digital Circuit Design Implementation)
Basic Design Synthesis Training (Digital Circuit Design Implementation)
I wonder if there has ever been such a detailed and clean explanation in semiconductor design field lectures.. Thank you so much for such a great video. The flow that actually takes place in design houses.. Above all, a video that explains so kindly in Korean.. It was so precious and welcome. You explain calmly and it goes right into my ears, so I think I'll recommend it to others as well. I think this would be a perfect lecture for those who are just starting out in semiconductor design. Thank you once again for the high-quality lecture! I think I'll be waiting to see if another lecture gets uploaded~
pa0202711
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Basic Design Synthesis Training (Digital Circuit Design Implementation)
Basic Design Synthesis Training (Digital Circuit Design Implementation)
Semiconductor design always felt difficult and distant to me, but this lecture completely changed my perspective. At first, the terminology was unfamiliar and I couldn't grasp the flow well, but as the instructor explained everything step by step in an easy way, I naturally began to understand.. Thanks to this, I became interested in this field and felt like I wanted to study it more. I'm really grateful that you made content I thought was just difficult so interesting!!
obc8646521889
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Basic Design Synthesis Training (Digital Circuit Design Implementation)
Basic Design Synthesis Training (Digital Circuit Design Implementation)
I am a SoC Physical Design Engineer. I work in the ASIC industry, and I took this course to understand the work of Front End during collaboration with Front End Engineers for Tapeout. Furthermore, it seems good that I was able to acquire knowledge about RTL Design as well. Since I listened to it during my free time, it felt healing. You explained things calmly and well, and I was able to refresh points that I had been missing in my mind. There were things I was curious about regarding the Tape-Out Flow, and there were new things I learned, which was great. I think this will be a good reference for my future work performance. Thank you.
rlaalswo8132670
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Basic SystemVerilog Testbench (Circuit Design Verification)
Basic SystemVerilog Testbench (Circuit Design Verification)
I think this is a lecture with content that's not easily accessible elsewhere. It was great to have detailed content on topics like test coverage, how to set up actual environments, and what to do if tools aren't available. It was a good lecture that came at just the right time when I was considering switching my career from Verilog design to SystemVerilog verification.
frioct
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Basic SystemVerilog Testbench (Circuit Design Verification)
Basic SystemVerilog Testbench (Circuit Design Verification)
It was a beneficial lecture where I could learn about System Verilog.
ysw9411217848
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Basic SystemVerilog Testbench (Circuit Design Verification)
Basic SystemVerilog Testbench (Circuit Design Verification)
It was really great to be able to learn SystemVerilog in such detail. I had been looking for an easy and detailed lecture but couldn't find one, then I came across this course. I could get a general understanding of the content from the table of contents, and the explanations about the topics and what would be discussed at the beginning helped me understand better. Also, by introducing an environment where I could run the corresponding code, I was able to run the testbench I wrote. This allowed me to see the results, making it more relatable. Furthermore, there were detailed explanations about the Design for DUT, so I could understand what verification work actually verifies. I've only listened to a little bit of the lecture so far, but I'm really satisfied up to this point.