Converting a Register Transfer Level design written in an HDL such as Verilog into a Gate Level design.
During the conversion process, the design is optimized according to constraints known as Synopsys Design Constraints.
Finally mapping to standard cells provided by the foundry.
Synthesis is the first gateway connecting the abstract and physical stages.
Ultimately, understanding synthesis means understanding the overall circuit design process.
In the industry, companies prefer new employees with experience in synthesis and timing verification.
However, because the related tools are expensive and inaccessible, it is a difficult field to study in school or through self-teaching.
In this course, you can experience the Design Compiler-based synthesis process used in the industry step-by-step,
and it explains many concepts used in circuit implementation roles beyond just synthesis.
Section 1. Basic Digital Logic Circuit concepts required for synthesis
Digital System
Timing concepts
Section 2. Detailed understanding of the Digital Chip Design Flow
SoC / ASIC
Physical Implementation (Front-End) / Physical Design (Back-End) Flow
Section 3. Understanding synthesis using Synopsys Design Compiler, the most widely used synthesis tool in the industry
Design Setup
Synopsys Design Constraints (SDC)
Synthesis Techniques
Timing Analysis
Preparation process required for synthesis
Understanding SDC commands for design optimization
Timing Concepts and Analysis
Various techniques in the compile process
Understanding of terms used in practice
Since this is the process of mapping Digital Design into "physical" gates, the following prerequisite knowledge is required:
Digital Logic Circuits
CMOS operating principles
Basic knowledge of the Verilog language
Linux environment
While it is not a requirement for the course content, the Linux environment is used across all practical work in the industry.
TCL for communicating with EDA tools
Similarly, it is not mandatory, but it is recommended to study it in your spare time.
TCL, the most widely used scripting language in the PI / PD field
What if you want to try hands-on practice after taking the lecture?
Inflearn Challenge Course [2-Week Synthesis Practice Challenge] is currently running (First 5 people per batch)
3rd Batch Recruitment in Progress: https://inf.run/ePpjr
This is a great opportunity to try out Synopsys' Design Compiler.
I wonder if there has ever been such a detailed and clean explanation in semiconductor design field lectures.. Thank you so much for such a great video. The flow that actually takes place in design houses.. Above all, a video that explains so kindly in Korean.. It was so precious and welcome. You explain calmly and it goes right into my ears, so I think I'll recommend it to others as well. I think this would be a perfect lecture for those who are just starting out in semiconductor design. Thank you once again for the high-quality lecture! I think I'll be waiting to see if another lecture gets uploaded~
This course was very helpful in systematically understanding everything from digital logic circuits to the synthesis process. Each section is structured step-by-step, making it easy for beginners to follow the flow, and the clear explanations of concepts frequently encountered in practice made it easy to understand. The explanations of timing analysis and the synthesis process were particularly useful enough to be directly applicable to actual work. The balance between examples and explanations was well-maintained, allowing me to learn complex content without feeling overwhelmed. Thank you for the great course.
Semiconductor design always felt difficult and distant to me, but this lecture completely changed my perspective. At first, the terminology was unfamiliar and I couldn't grasp the flow well, but as the instructor explained everything step by step in an easy way, I naturally began to understand.. Thanks to this, I became interested in this field and felt like I wanted to study it more. I'm really grateful that you made content I thought was just difficult so interesting!!
I am a SoC Physical Design Engineer. I work in the ASIC industry, and I took this course to understand the work of Front End during collaboration with Front End Engineers for Tapeout. Furthermore, it seems good that I was able to acquire knowledge about RTL Design as well. Since I listened to it during my free time, it felt healing. You explained things calmly and well, and I was able to refresh points that I had been missing in my mind. There were things I was curious about regarding the Tape-Out Flow, and there were new things I learned, which was great. I think this will be a good reference for my future work performance. Thank you.
