Design Self-Study Tastebi's Practical Verilog HDL Season 1 (From Clock to Internal Memory)

"Students may find the price burdensome at first, but the more you listen, the more you realize that it is worth the price paid." I have completed the Pipeline course. I can't help but want to write a good review quickly, so I am writing it in advance. I am about to graduate, but I was mentally exhausted due to passing the preliminary exam for a large company in the second half of the year. I started taking the course with a light heart, thinking, "Let's study FPGA/Verilog, which is preferred by the job, and appeal to the next application", but this course really got me interested in this field. (+The explanations that are easy to understand, and the process of understanding them one by one while persistently sticking to them, even though it is difficult, are really interesting.) I want to quickly and thoroughly practice hard and reach a level where I can design things myself just by looking at the specs. After that, I want to quickly do various practical exercises and projects using FPGA. Thank you for providing such a high-quality course, Mr. Matbi.

This was a lecture that I couldn't help but give 5 points to. It was great because the content was explained in detail and if there was something I didn't know, I could quickly answer questions (of course, if you Google or refer to other students' questions, most problems can be solved.). In particular, since Matbi's computer environment and mine were different, it was difficult to install vivado, but thanks to the quick feedback, I was able to install it without any problems. And I think you uploaded a new version of vivado installation video, which is really great. Please stay healthy and teach for a long time in the future!

This is a lecture that I highly recommend to those who are interested in Verilog and non-memory design. Mr. Matbi is very good at answering even the smallest questions and giving quick feedback, so I had no inconvenience in taking the class. However, I do not recommend this to people who do not even know the v in Verilog grammar. I remember being confused when I first took the class in this state because there was almost no explanation of Verilog grammar. Mr. Matbi explains it roughly, but it will be helpful if you know the basic Verilog grammar. On the other hand, I think it will be very helpful to those who have taken a Verilog class at school or have studied Verilog personally. It covers only the core content that I could not learn at school or while studying alone. This is a comprehensively recommended lecture.

There are external classes like IDEC or SW-SOC, but in the case of IDEC, since the two professors try to convey a lot of content concisely, there are many cases where it is difficult to understand. But you can't watch it again. In the case of SW-SOC, it's a seasonal system? You register for the lecture (I don't know why you have to register for the lecture when they just repeat what was taught before in the case of online lectures). They are either very job-related lectures or very simple lectures. Honestly, reading the book is more helpful. This person's lecture is explained based on example code from the perspective of a current employee, so it's understandable and it really helped me a lot when designing FPGAs. Highly recommended! Thank you, Matbi.

I learned the basics of H/W design using Verilog and what direction to study. Thank you.

I enjoyed the lecture. I hope you continue to give great lectures in the future.

It took a whole day to install and I just registered and started listening, but I am really grateful that you uploaded a lecture on Verilog that I can listen to at any time. I think that this lecture is definitely worth 200,000-300,000 won, and I will definitely listen to the next lecture. If you happen to film all the FPGA roadmap lectures, I will also run to the end.!!

There is no substitute.