About MetaEncore - Inflearn

MetaEncore

@metaencorehr

Students

149

Reviews

Course Rating

4.7

AI(Artificial Intelligence)와 IoT(Internet of Things) 등 주문형 chip(ASIC, application-specific integrated circuit)에 대한 시장의 요구는 늘어나고 있고, 실제로 많은 chip들이 설계되고 있으나, 실질적인 삶의 변화로까지 이어지지는 경우는 드뭅니다.

많은 ASIC 설계들이 기능적으로 오류가 있거나, 계획하였던 성능 조건을 만족시키지 못하기 때문입니다. 좋은 반도체를 만들어서 우리의 삶을 좀 더 윤택하게 하려면, 규모가 커지고 복잡해진 설계를 다룰 수 있는 고도화된 기능 및 성능 검증을 제공하기 위한 서비스가 필요합니다. 메타앙코르는 그러한 서비스를 제공함으로써 사람을 이롭게 하는 반도체가 많아지는 것을 목표로 하는 회사입니다.

Courses

Reviews

seanok959237
·
[2-Week Synthesis Practice Challenge 4th Class] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)
[2-Week Synthesis Practice Challenge 4th Class] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)
The text is too small to follow along with the practice, making it difficult to keep up.

ghdrlqls116797
·
Basic UVM Testbench (Circuit Design Verification)
Basic UVM Testbench (Circuit Design Verification)
It seems like a great lecture. However, it would be nice if the lecture materials were available for download.

wwa99819313
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Basic SystemVerilog Testbench (Circuit Design Verification)
Basic SystemVerilog Testbench (Circuit Design Verification)
This was a lecture where I could review the basics of SystemVerilog that I already knew, while also discovering parts I hadn't known before.

laylar00217581
·
Basic UVM Testbench (Circuit Design Verification)
Basic UVM Testbench (Circuit Design Verification)
I think I will be able to build a solid foundation in UVM.

somisomisomsomi
·
Basic UVM Testbench (Circuit Design Verification)
Basic UVM Testbench (Circuit Design Verification)
I listened to this because I wondered if there would be any overlap with the previous SystemVerilog lecture, and it was great because the content went further and included additional explanations. I think it's a good way to build a foundation in UVM.

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