Learning RISC-V Architecture Through Debugging - Part 2

1. To commemorate the launch of Korea's first RISC-V course, we are issuing a 30% discount coupon (first come, first served for 100 people).

Coupon link: https://inf.run/Yh8vb

2. 2025 Latest Course Renewal

We've discovered the latest RISC-V architecture features and valuable content that can be directly applied to real-world projects, and have added the following courses.

• 'Synchronous Exception Behavior' session added (4 lectures) - 07/23 (2025)

In the latest system software industry
the emerging RISC-V architecture

Recently, the RISC-V architecture, an open-source-based CPU architecture, has been emerging. If you look at IT-related press articles or news, you can immediately see the following content:

• nVidia, Intel, and Qualcomm, among other big tech companies, are developing RISC-V-based products (chipsets).

• The number of startup companies in Korea designing various chips using RISC-V is increasing, and the proportion of developing products based on RISC-V devices is growing.

• RISC-V-based CPU architectures are widely utilized when designing AI semiconductors.

• By 2026, 15 billion devices are expected to be released based on RISC-V.

• In graduate school (processor design), various research is being conducted using toolkits that can design RISC-V CPUs.

The proportion of embedded and system software companies developing products using RISC-V CPU architecture is increasing. Therefore, job seekers need to prepare for RISC-V-related questions in technical interviews as well.

Background of Creating the Course

From a beginner's perspective, RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what's important among the vast content that makes up RISC-V

• I'm not sure which features among the components that make up RISC-V are utilized in real-world projects

• No matter how hard you read the RISC-V specification document, it's difficult to understand right away

  
  

• It's difficult to understand what the term RISC-V itself means when explaining RISC-V

  
  

Compared to the Arm architecture, there is insufficient material related to the RISC-V architecture, and the reality is that there is a lack of resources that explain RISC-V concretely and easily. This course was created to address the difficulties that system software developers, including new developers, experience in the process of learning RISC-V.

Course Structure and Part 1, Part 3 Course Roadmap

This lecture covers the content of Part 2, which deals with the core functionality of RISC-V, from the complete RISC-V lecture series.

• Part 1: RISC-V Introduction, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture through Debugging Part 1)

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling Convention

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension (Learning RISC-V Architecture through Debugging Part 3)

  
  

You can check the complete RISC-V architecture lecture in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Course

You'll learn this kind of content 📕

This provides a detailed explanation of the basic concepts of exceptions and clearly explains the core features of exceptions defined in the RISC-V architecture.

This explains the execution flow of exceptions, which is a core feature of the RISC-V architecture. It also provides a detailed explanation of how exceptions are handled in a system composed of machine mode and user mode.

Explains the exception code defined in the RISC-V architecture that indicates the cause of the exception, and describes the flow diagram of how exceptions are handled through memory abort.

From a software development perspective, this provides a detailed explanation of the execution flow when exceptions and crashes are triggered.

We analyze assembly instructions line by line to explain what flow triggers exceptions. We also explain how exceptions are handled on the stack when they occur.

Practice exceptions using the T32 debugging practice program by executing assembly instructions. When exceptions are triggered, provide detailed explanations of which CSR (scause, mcause) registers are modified.

We will conduct hands-on practice using the TRACE32 program to trigger exceptions, while providing detailed explanations of exception handlers processed in the Linux kernel.

Analyzing memory dumps from RISC-V based boards, this explains how exceptions work in the RISC-V architecture: analyzing kernel logs and call stacks.

We will conduct debugging practice on page tables using the TRACE32 program. Through this, we will specifically identify the causes that triggered the exception.

This explains the basic operation of interrupt controllers defined in the RISC-V architecture. It provides an easy-to-understand explanation of the structure of PLIC and CLIC.

Review interrupt-related exception code and explain the structure of PLIC (Platform Level Interrupt Controller).

Explains the core hardware components that make up the PLIC and provides an easy-to-understand explanation of the CSR registers that control the PLIC.

This explains the Calling Convention (function calling convention) introduced in the RISC-V architecture and reviews the registers that support the Calling Convention.

Explains the big picture of how arguments passed to functions are processed.

Analyzing the assembly instructions that support the Calling convention (function calling convention) of the RISC-V architecture. Also analyzing example assembly instructions - c.sdsp instruction analysis

Analyzing the RISC-V architecture's Calling convention (function calling convention) supporting assembly instructions. Also analyzing example assembly instructions - c.ldsp instruction analysis

Analyzing the RISC-V architecture's Calling convention (function calling convention) supporting assembly instructions. Also analyzing example assembly instructions - c.ldsp instruction analysis

We will conduct a hands-on practice session to restore broken call stacks using TRACE32 debugging.

We will analyze memory dumps caused by stack overflow through TRACE32 debugging practice.

Based on book writing/teaching experience
Deeper and more detailed than anyone else!

In the domestic system software field, unprecedented! Author who wrote books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books selected as excellent books by the Korean Academy), and the first in Korea to write "Reverse Engineering Armv8-A Systems" book (in English) through an overseas publisher (Packt), making them a global author. Above all, they are a current industry developer who best understands the latest system software trends (electric vehicles, system semiconductors - system software). They are also an educator who is most actively engaged in knowledge dissemination activities in the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' book (English) author, (Packt Publishing)

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024 Korea Academy Outstanding Book Award)

• 'Learning Linux Kernel Structure and Principles Through Debugging' (2021 Korea Academy Outstanding Book Award) Author

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor (including domestic and overseas developers) - (2020~2024)