RISC-V Architecture Through Debugging - Part 2

In the modern systems software industry
The Emerging RISC-V Architecture

Recently, the RISC-V architecture, an open source-based CPU architecture, is on the rise. If you look at IT-related media articles or news, you can immediately see the following:

• Big tech companies like nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startup companies designing various chips using RISC-V in Korea is increasing, and the proportion of products developed based on RISC-V devices is increasing.

• When designing AI semiconductors, RISC-V-based CPU architecture is widely used.

• 15 billion devices are expected to be RISC-V-based by 2026.

• In the graduate school (processor design), various studies are being conducted using a toolkit that can design RISC-V CPUs.

Embedded and system software companies are increasingly developing products using RISC-V CPU architectures, so job seekers need to prepare for RISC-V during technical interviews.

Background on creating the lecture

For beginners, the RISC-V architecture is difficult to learn. Here are some reasons why:

• I don't know what is important among the vast content that makes up RISC-V.

• I don't know which functions of RISC-V are used in real projects.

• No matter how hard you read the RISC-V specification document, it is difficult to understand it right away.

  
  

• It is difficult to know what the term itself that describes RISC-V means.

  
  

Compared to the Arm architecture, there is not enough information on the RISC-V architecture, and there is a lack of information that specifically and easily explains RISC-V. I created this lecture to help system software developers, including new developers, overcome the difficulties they face when learning RISC-V.

Key differentiating points of the lecture

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It explains the basic concepts of exceptions in detail and provides an easy-to-understand explanation of the core features of exceptions defined in the RISC-V architecture.

Describes the execution flow of exceptions, a core feature of the RISC-V architecture. It also explains in detail how exceptions are handled in a system consisting of machine mode and user mode.

Describes the exception codes that indicate the cause of the exception as defined in the RISC-V architecture, and also explains the flow of exception handling with memory abort.

From a software development perspective, it details the execution flow when exceptions and crashes occur.

It explains the flow of exceptions by analyzing assembly instructions line by line. It also explains how exceptions are handled on the stack when they occur.

Practice exceptions by executing assembly instructions with the T32 debugging practice program. It explains in detail which CSR (scause, mcause) registers are changed when an exception is triggered.

We will explain in detail the exception handler processed in the Linux kernel while practicing causing an exception with the TRACE32 program.

By analyzing a memory dump obtained from a RISC-V based board, we explain how exceptions work in the RISC-V architecture: analyze the kernel log, analyze the call stack.

We will practice debugging page tables using the TRACE32 program. This will help us to understand specifically what caused the exception.

Describes the basic operation of the interrupt controller defined in the RISC-V architecture. Explains the structure of PLIC and CLIC in an easy-to-understand manner.

We review exception codes related to interrupts and explain the structure of the Platform Level Interrupt Controller (PLIC).

Describes the core hardware components that make up a PLIC and provides an easy-to-understand explanation of the CSR registers that control the PLIC.

We will explain the Calling Convention introduced in the RISC-V architecture and review the registers that support the Calling Convention.

Explains the big picture of how arguments passed to a function are processed.

Analyze assembly instructions that support the calling convention of RISC-V architecture. Also analyze example assembly instructions - c.sdsp instruction analysis.

Analyze assembly instructions that support the calling convention of the RISC-V architecture. Also analyze example assembly instructions - c.ldsp instruction analysis.

Analyze assembly instructions that support the calling convention of the RISC-V architecture. Also analyze example assembly instructions - c.ldsp instruction analysis.

We will go through a hands-on exercise to restore a broken call stack using TRACE32 debugging.

In this TRACE32 debugging exercise, we will analyze a memory dump caused by a stack overflow.

Based on my experience writing books and giving lectures
More in-depth and detailed than anyone else!

The author of the unprecedented 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' books in the domestic system software field. He is also a working developer who knows the latest system software trends (electric vehicles, system semiconductors - system software) the best, and an educator who is most active in spreading knowledge in the system software field.

• Author of 'Structure and Principles of Arm Architecture for System Software Development' ( 2024, Korean Academy of Sciences Outstanding Book Award )

• Author of 'Learning the Structure and Principles of the Linux Kernel through Debugging' ( 2021, Korean Academy of Sciences Outstanding Book Award )

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Conference (KCC2022) - Tutorial presentation [Conquering the Linux Kernel using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor ( including domestic and overseas developers ) - (2020~2024)