Learning RISC-V Architecture with Debugging - Part 3

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In the latest system software industry
the emerging RISC-V architecture

Recently, the RISC-V architecture, an open source-based CPU architecture, has been emerging. If you look at IT-related press articles or news, you can immediately see the following content:

• nVidia, Intel, and Qualcomm, among other big tech companies, are developing RISC-V-based products (chipsets).

• The number of startup companies in Korea designing various chips using RISC-V is increasing, and the proportion of developing products based on RISC-V devices is growing.

• AI semiconductors often utilize RISC-V-based CPU architectures in their design.

• By 2026, 15 billion devices are expected to be released based on RISC-V.

• In graduate school (processor design), various research is being conducted using toolkits that can design RISC-V CPUs.

The proportion of embedded and system software companies developing products using RISC-V CPU architecture is increasing. Therefore, job seekers need to prepare for RISC-V-related questions in technical interviews.

Background of Creating the Course

From a beginner's perspective, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what's important among the vast content that makes up RISC-V

• I'm not sure which features among the components that make up RISC-V are utilized in real-world projects

• No matter how hard you read the RISC-V specification document, it's difficult to understand right away

  
  

• It's difficult to understand what the term RISC-V itself means when explaining RISC-V

  
  

This lecture is the third lecture in the Learning RISC-V Architecture through Debugging series, covering content to become a system software developer capable of earning a high salary beyond the beginner level - explaining memory systems (virtual memory, memory barriers, cache) and Hypervisor Extension features.

Course Structure and Part 2, Part 3 Lecture Roadmap

This lecture covers the content of Part 3, which deals with the core functionality of RISC-V, from the complete RISC-V lecture series.

• Part 1: RISC-V Introduction, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture Through Debugging Part 1)

• Part 2: Exception (Memory Abort Exception), Interrupt, PLIC (Platform-level Interrupt Controller), Calling convention (Learning RISC-V Architecture through Debugging Part 2)

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor Extension

  
  

You can check the complete RISC-V architecture lecture in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Course

You'll learn this content 📕

This introduces the key memory features of the RISC-V architecture and also introduces the core functions that make up the virtual memory system. It explains them in an easy-to-understand way with the big picture.

This introduces the virtual memory map, which is the core of the virtual memory system. It also provides an easy-to-understand explanation of the virtual address ranges for kernel space and user space.

This explains the satp register that sets up the page table and provides an easy-to-understand explanation of virtual address concepts through memory dump debugging practice. (Memory dumps are provided in the course materials.)

Explains the concepts of virtual addresses and page tables, and describes the range of virtual addresses through actual case studies.

Explains the structure of multi-level page tables and provides a detailed explanation of PTE (Page Table Entry).

This provides a detailed explanation of the process of directly converting virtual addresses to physical addresses through multi-level page tables. It also includes debugging practice using the Crash Utility program to convert virtual addresses to physical addresses.

This provides a detailed explanation of MMU operation from a hardware design perspective while analyzing the MMU specifications of SiFive's U74 core and P550 core.

Explains memory reordering and provides an easy-to-understand explanation of how fence instructions work to prevent memory reordering.

Explains the basic structure (form) of the fence command and describes in detail how the fence command operates with various options applied.

This explains how fence instructions operate in multi-core system environments - analyzing the principles by which fence instructions synchronize with other cores when executed. It also explains fence instructions while analyzing example assembly commands.

Introduces the fence.i instruction and explains the overall flow of what happens when the fence.i instruction is executed from a big picture perspective.

We analyze the fence.i instruction by examining various example assembly routines. We analyze the fence.i instruction while comparing it with the Arm architecture.

Explains the basic concepts of cache and also explains why cache is used.

Explains the operating principles of cache in multi-core systems and analyzes the key features of cache defined in RISC-V while comparing with Arm architecture.

Explains the basic elements that make up a cache and provides a detailed explanation of how addresses are processed during cache lookup (the process of searching through the cache).

Introduces hypervisors and explains the Privilege mode in which the Hypervisor runs in the RISC-V architecture.

This introduces the core features of the Hypervisor Extension defined in the RISC-V architecture and explains how to activate the Hypervisor Extension.

When an exception is triggered in the Guest OS, the Hypervisor takes control first, explaining the execution flow.

Based on book writing/teaching experience
Deeper and more detailed than anyone else!

In the domestic system software field, this is an unprecedented! author who wrote books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books were selected as excellent books by the Korean Academy), and is a global author who was the first in Korea to write the book "Reverse Engineering Armv8-A Systems" (in English) through an overseas publisher (Packt). Above all, they are a working developer who best understands the latest system software trends (electric vehicles, system semiconductors - system software). They are also an educator who is most actively engaged in knowledge dissemination activities in the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' book (English) author, (Packt Publishing)

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024 Korea Academy Outstanding Book Award)

• 'Learning Linux Kernel Structure and Principles Through Debugging' (2021 Korea Academy Outstanding Book Award) Author

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor (including domestic and overseas developers) - (2020~2024)