Learning the RISC-V Architecture Through Debugging - Part 3

Announcement 🎯

To celebrate the launch of the first RISC-V course in Korea, we are issuing 30% discount coupons (first 100 people).

Coupon Link: https://inf.run/rGFpZ

In the latest system software industry,
the emerging RISC-V architectuređang nổi lên

Recently, the RISC-V architecture, an open-source-based CPU architecture, has been emerging. You can immediately see content like the following in IT-related media articles or news:

• Big tech companies such as nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startups in Korea designing various chips using RISC-V is increasing, and the proportion of developing products based on RISC-V devices is rising.

• When designing AI semiconductors, the RISC-V-based CPU architecture is widely utilized.

• It is expected that 15 billion RISC-V-based devices will be released by 2026.

• Graduate schools (processor design) are conducting various research projects using toolkits capable of designing RISC-V CPUs.

Embedded and system software companies are increasingly utilizing the RISC-V CPU architecture to develop their products. As a result, job seekers now need to prepare for RISC-V even during technical interviews.

Background of creating this course

From a beginner's perspective, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what is important among the vast amount of content that makes up RISC-V.

• I don't know which features among the contents that make up RISC-V are actually utilized in real-world projects.

• No matter how hard you read the RISC-V specification documents, it is difficult to understand them immediately.

  
  

• It is difficult to understand what the terms used to explain RISC-V actually mean.

  
  

This course is the third lecture in the RISC-V Architecture series learned through debugging. It covers content designed to help you go beyond the beginner level and become a system software developer capable of earning a high salary—explaining memory systems (virtual memory, memory barriers, cache) and Hypervisor Extension features.

A lecture by a RISC-V expert proven through global practical experience

1. Linux Plumbers Conference Presentation: Debugging RISC-V Kernel Crashes (December 2025)

(Source: https://www.youtube.com/watch?v=LNih2OdEcYo&t=1s)

2. Book: Practical Debugging for Embedded RISC‑V (Global Packt Publishing - Scheduled for publication in November 2026)

(Source: https://www.amazon.com/Practical-Debugging-Embedded-RISC%E2%80%91V-RISCV-Based/dp/1806699354/)

Course Structure and Roadmap for Part 2 and Part 3

This lecture covers the content of Part 3, which focuses on the core features of RISC-V, out of the entire RISC-V lecture series.

• Part 1: Introduction to RISC-V, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture through Debugging Part 1)

• Part 2: Exception (Memory Abort Exception), Interrupt, PLIC (Platform-level Interrupt Controller), Calling convention (Learning RISC-V Architecture through Debugging Part 2)

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension

  
  

The full RISC-V architecture course can be found in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Lecture

What you will learn 📕

We introduce the key memory features of the RISC-V architecture and the core functions that make up the virtual memory system. We explain them in an easy-to-understand manner along with the big picture.

We introduce the virtual memory map, which is the core of the virtual memory system. Additionally, we provide an easy-to-understand explanation of the virtual address ranges for both kernel space and user space.

We explain the satp register, which sets up the page table, and provide an easy-to-understand explanation of virtual address concepts through a memory dump debugging practice session. (The memory dump is provided in the lecture materials.)

It explains the concepts of virtual addresses and page tables, and describes the range of virtual addresses through actual case studies.

It explains the structure of multi-level page tables and provides a detailed explanation of the PTE (Page Table Entry).

We explain in detail the process of directly translating virtual addresses to physical addresses through multi-level page tables. We also conduct a debugging practice session using the Crash Utility program to convert virtual addresses into physical addresses.

While analyzing the MMU specifications of SiFive's U74 and P550 cores, we will explain the operation of the MMU in detail from a hardware design perspective.

It explains memory reordering and provides an easy-to-understand explanation of the operating principles of fence instructions that prevent memory reordering.

Explain the basic structure (form) of the fence instruction and provide a detailed explanation of how the fence instruction operates when various options are applied.

Explains how the fence instruction operates in a multi-core system environment - analyzes the principles of how synchronization with other cores occurs when the fence instruction is executed. Additionally, explains the fence instruction while analyzing example assembly instructions.

Introduces the fence.i instruction and explains the overall processing flow when the fence.i instruction is executed.

We analyze the fence.i instruction by examining various example assembly routines. We also analyze the fence.i instruction while comparing it with the Arm architecture.

It explains the basic concepts of cache and also explains why cache is used.

Explain the operating principles of caches in multi-core systems and analyze the core features of caches defined in RISC-V while comparing them with the Arm architecture.

It explains the basic elements that make up a cache and provides a detailed explanation of how addresses are processed during a cache lookup (the process of searching the cache).

Introduces the hypervisor and explains the privilege mode in which the hypervisor runs in the RISC-V architecture.

It introduces the core features of the Hypervisor Extension defined in the RISC-V architecture and explains how to enable the Hypervisor Extension.

It explains the execution flow where the Hypervisor first takes control when an exception is triggered in the Guest OS.

Based on my experience writing books and lecturing,
deeper and more detailed than anyone else!

An unprecedented author in the domestic system software field who has written books on the 'Arm Architecture (Armv8-A, Armv7-A)' and the 'Linux Kernel' (both books were selected as Excellent Academic Books by the National Academy of Sciences, Republic of Korea), and a global author who is the first in Korea to write the book "Reverse Engineering Armv8-A Systems" (in English) through an overseas publisher (Packt). Above all, he is an active developer who is most well-versed in the latest system software trends (electric vehicles, system semiconductors - system software). He is also an educator who is most actively engaged in spreading knowledge within the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' Author (English), (Packt Publishing)

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024, National Academy of Sciences Outstanding Book Award)

• 'Structure and Principles of the Linux Kernel Learned Through Debugging' (2021, National Academy of Sciences Excellent Scholarly Book Award) Author

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor (Including domestic and overseas developers) - (2020~2024)