Learning RISC-V Architecture through Debugging - Part 3

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To celebrate the launch of Korea's first RISC-V course, we're issuing a 30% discount coupon (limited to the first 100 people).

Coupon link: https://inf.run/rGFpZ

Rising in the latest system software industry
RISC-V Architecture

Recently, RISC-V architecture, an open-source based CPU architecture, has been emerging. You can immediately see the following content in IT-related press articles and news:

• Big tech companies like nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startup companies designing various chips using RISC-V is increasing domestically, and the proportion of developing RISC-V device-based products is growing.

• When designing AI semiconductors, RISC-V-based CPU architectures are widely utilized.

• By 2026, 15 billion devices are expected to be released based on RISC-V.

• Graduate schools (processor design) are conducting various research using toolkits that can design RISC-V CPUs.

The proportion of embedded and system software companies developing products using RISC-V CPU architecture is increasing. As a result, job seekers need to prepare for RISC-V in technical interviews as well.

Background of Creating This Course

For beginners, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what's important among the vast amount of content that makes up RISC-V

• I don't know which features among the components that make up RISC-V are actually used in real-world projects

• Even if you read the RISC-V specification documents diligently, they are difficult to understand right away

  
  

• It's difficult to understand what the terms used to explain RISC-V actually mean

  
  

This course is the third course in the Learning RISC-V Architecture through Debugging series, covering content to become a system software developer at a level that can command a high salary beyond beginner level - explaining memory systems (virtual memory, memory barriers, cache) and Hypervisor Extension features.

Course Structure and Roadmap for Parts 2 and 3

This lecture covers Part 3 of the complete RISC-V lecture series, which deals with the core features of RISC-V.

• Part 1: RISC-V Introduction, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture through Debugging Part 1)

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling convention (Learning RISC-V Architecture through Debugging Part 2)

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension

  
  

You can check the complete RISC-V architecture course in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Course

Here's what you'll learn 📕

I introduce the key memory features of the RISC-V architecture and the core functions that make up the virtual memory system. I explain them in an easy-to-understand way with the big picture.

Introduces the virtual memory map, which is the core of the virtual memory system. Also provides an easy-to-understand explanation of the virtual address ranges for kernel space and user space.

This explains the satp register that configures the page table, and clearly explains the concept of virtual addresses through memory dump debugging practice. (Memory dumps are provided in the course materials.)

Explains the concepts of virtual addresses and page tables, and describes the range of virtual addresses through actual case studies.

It explains the structure of multi-level page tables and provides a detailed explanation of PTE (Page Table Entry).

It explains in detail the process of directly translating virtual addresses to physical addresses through multi-level page tables. It also includes a debugging exercise using the Crash Utility program to convert virtual addresses to physical addresses.

While analyzing the MMU specifications of SiFive's U74 core and P550 core, it provides a detailed explanation of how the MMU operates from a hardware design perspective.

We explain memory reordering and provide an easy-to-understand explanation of how the fence instruction works to prevent memory reordering.

Explains the basic structure (form) of the fence instruction and provides detailed explanations of how the fence instruction operates with various options applied.

Explains how the fence instruction operates in a multi-core system environment - analyzes the principle by which synchronization occurs with other cores when the fence instruction is executed. Also explains the fence instruction while analyzing example assembly instructions.

This section introduces the fence.i instruction and explains the overall flow of how it is processed when executed.

We analyze the fence.i instruction while examining various example assembly routines. We analyze the fence.i instruction by comparing it with the Arm architecture.

It explains the basic concepts of cache and why cache is used.

It explains the operating principles of cache in multi-core systems and analyzes the key cache features defined in RISC-V while comparing them with the Arm architecture.

It explains the basic components that make up a cache and provides a detailed explanation of how addresses are processed during cache lookup (the process of searching the cache).

Introduces the hypervisor and explains the Privilege mode in which the Hypervisor runs in the RISC-V architecture.

It introduces the core features of the Hypervisor Extension defined in the RISC-V architecture and explains how to enable the Hypervisor Extension.

When an exception is triggered in the Guest OS, it explains the execution flow where the Hypervisor controls it first.

Based on book writing/teaching experience
More in-depth and detailed than anyone else!

Unprecedented in Korea's system software field! An author who has written books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books selected as Outstanding Academic Books by the National Academy of Sciences of the Republic of Korea), and the first in Korea to publish "Reverse Engineering Armv8-A Systems" (in English) through an international publisher (Packt), making them a global author. Above all, they are a current industry developer who best understands the latest system software trends (electric vehicles, system semiconductors - system software). They are also an educator who is most actively engaged in knowledge dissemination activities in the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' book (English) author, (Packt Publishing)

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024 Korea Academy Award for Outstanding Books)

• Author of 'Learning Linux Kernel Structure and Principles through Debugging' (2021 National Academy of Sciences Outstanding Book Award)

• Main instructor for 'Programmers Dev Course: Linux System and Kernel Expert'

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Mastering the Linux Kernel with ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' in-house instructor (domestic and international developers included) - (2020~2024)