Learning RISC-V Architecture through Debugging - Part 1

Notice 🎯

To commemorate the launch of Korea's first RISC-V course, we are issuing 30% discount coupons (first come, first served for 100 people).

Coupon Link: https://inf.run/tTzGm

In the latest system software industry,
the emerging RISC-V architecture

Recently, the RISC-V architecture, an open-source-based CPU architecture, has been gaining prominence. When looking at IT-related press articles or news, you can immediately see content like the following:

• nVidia, Intel, and Qualcomm, among other big tech companies, are developing RISC-V-based products (chipsets).

• The number of startup companies in Korea designing various chips using RISC-V is increasing, and the proportion of developing products based on RISC-V devices is growing.

• When designing AI semiconductors, RISC-V-based CPU architectures are frequently utilized.

• By 2026, 15 billion devices are expected to be released based on RISC-V.

• In graduate school (processor design), various research is being conducted using toolkits that can design RISC-V CPUs.

The proportion of embedded and system software companies developing products using RISC-V CPU architecture is increasing. Therefore, job seekers need to prepare for RISC-V-related questions in technical interviews as well.

Background of Creating the Course

From a beginner's perspective, RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what's important among the vast content that makes up RISC-V

• I'm not sure which features among the components that make up RISC-V are utilized in real-world projects

• No matter how hard you read the RISC-V specification document, it's difficult to understand right away

  
  

• It's difficult to understand what the term RISC-V itself means when explaining RISC-V

  
  

Compared to the Arm architecture, there is insufficient material related to the RISC-V architecture, and the reality is that there is a lack of resources that explain RISC-V concretely and easily. This course was created to resolve the difficulties that system software developers, including new developers, experience in the process of learning RISC-V.

Course Structure and Part 2, Part 3 Lecture Roadmap

This lecture covers the content of Part 1, which deals with the core functions of RISC-V, from the complete RISC-V lecture series.

• Part 1: RISC-V Introduction, Registers, Assembly Instructions, Privilege Mode

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling Convention (Learning RISC-V Architecture through Debugging Part 2)

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension (Learning RISC-V Architecture through Debugging Part 3)

  
  

You can check the complete RISC-V architecture course in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Course

You'll learn this content 📕

This explains each stage of system semiconductor development and introduces the development ecosystem related to RISC-V architecture.

This provides a detailed explanation of why you need to understand RISC-V architecture from a practical project perspective.

This provides a detailed explanation of registers, which are the core of the RISC-V architecture. It also explains how registers are utilized.

This introduces the types of registers, which are the core of the RISC-V architecture, and provides a detailed explanation of general-purpose registers.

This explains the basic functions and types of CSR (Control and Status) registers.

Explains in detail how to read and write CSR registers

The structure and operation of registers are explained through hands-on practice by running the TRACE32 educational program (simulator).

Explains the basic operation of assembly instructions and describes various assembly instructions. (Example: JAL instruction analysis)

Explains conditional branch instructions like BEQ in detail and covers how they are utilized in real-world projects.

We will conduct hands-on practice debugging assembly instructions using the TRACE32 simulator (educational version) program. (Instructors can also follow along and practice directly)

This provides a detailed explanation of the concept of Privilege Mode and its related Privilege Levels.

Analyzes the specifications related to Privilege Mode and explains what software runs in each Privilege Mode.

Based on book writing/teaching experience
Deeper and more detailed than anyone else!

In the domestic system software field, unprecedented! Author who wrote books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books selected as excellent books by the Korean Academy), and the first in Korea to write "Reverse Engineering Armv8-A Systems" book (in English) through an overseas publisher (Packt), making them a global author. Above all, they are a current industry developer who best understands the latest system software trends (electric vehicles, system semiconductors - system software). They are also an educator who is most actively engaged in knowledge dissemination activities in the system software field.

• Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis (Packt Publisher: English) - Published in 2025

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024 Korea Academy Outstanding Book Award)

• 'Learning Linux Kernel Structure and Principles Through Debugging' (2021 Korea Academy of Sciences Excellence in Books Award) Author

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor (including domestic and overseas developers) - (2020~2024)