Learning RISC-V Architecture through Debugging - Part 1

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To celebrate the launch of Korea's first RISC-V lecture, we are issuing a 30% discount coupon (for the first 100 people).

Coupon: 17338-22e9b70d6177

In the modern systems software industry
The Emerging RISC-V Architecture

Recently, the RISC-V architecture, an open source-based CPU architecture, is on the rise. If you look at IT-related media articles or news, you can immediately see the following:

• Big tech companies like nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startup companies designing various chips using RISC-V in Korea is increasing, and the proportion of products developed based on RISC-V devices is increasing.

• When designing AI semiconductors, RISC-V-based CPU architecture is widely used.

• 15 billion devices are expected to be RISC-V-based by 2026.

• In the graduate school (processor design), various studies are being conducted using a toolkit that can design RISC-V CPUs.

Embedded and system software companies are increasingly developing products using RISC-V CPU architectures, so job seekers need to prepare for RISC-V during technical interviews.

Background on creating the lecture

For beginners, the RISC-V architecture is difficult to learn. Here are some reasons why:

• I don't know what is important among the vast content that makes up RISC-V.

• I don't know which functions of RISC-V are used in real projects.

• No matter how hard you read the RISC-V specification document, it is difficult to understand it right away.

  
  

• It is difficult to know what the term itself that describes RISC-V means.

  
  

Compared to the Arm architecture, there is not enough information on the RISC-V architecture, and there is a lack of information that specifically and easily explains RISC-V. I created this lecture to help system software developers, including new developers, overcome the difficulties they face when learning RISC-V.

Lecture structure and roadmap for parts 2 and 3

This lecture covers Part 1, the core features of RISC-V, among the entire RISC-V lecture list.

• Part 1: Introduction to RISC-V, Registers, Assembly Instructions, Privilege Mode

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling convention ( Learning RISC-V Architecture through Debugging Part 2 )

• Part 3: Virtual memory system, cache, fence/barrier, hypervisor extension ( Learning RISC-V architecture through debugging, Part 3 )

  
  

The full RISC-V architecture lecture can be found in the Roadmap - ' RISC-V Architecture for System Software Developers ' lecture.

Key differentiating points of the lecture

Learn about these things 📕

We describe each step of developing a system semiconductor and introduce the development ecosystem related to the RISC-V architecture.

We will explain in detail from a practical project perspective why you need to know the RISC-V architecture well.

We will explain in detail about the registers, which are the core of the RISC-V architecture. We will also explain how the registers are utilized.

We introduce the types of registers that are the core of the RISC-V architecture and explain general-purpose registers in detail.

Describes the basic functions and types of the CSR (Control and Status) register.

Explains in detail how to read and write the CSR register.

The configuration and operation of registers are explained through practice by running the TRACE32 educational program (simulator).

Describes the basic operation of assembly instructions and describes various assembly instructions. (Example: Analysis of JAL instruction)

We explain conditional branch instructions such as BEQ and detail how they are used in real-world projects.

We will practice debugging assembly instructions using the TRACE32 simulator (educational) program. (Educators can also follow along and practice)

Explains in detail the concept of Privilege Mode and its related Privilege Level.

We analyze the specifications related to Privilege Mode and explain what software runs in each Privilege Mode.

Based on my experience writing books and giving lectures
More in-depth and detailed than anyone else!

Unparalleled in the domestic system software field ! Author of 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' ( both books selected as excellent books by the Korean Academy of Sciences ) and global author who wrote the book "Reverse Engineering Armv8-A Systems" (English) through a foreign publisher (Packt) for the first time in Korea . Above all, he is a working developer who knows the latest system software trends (electric vehicles, system semiconductors - system software) the best. He is also an educator who is most active in knowledge dissemination in the field of system software.

• Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis (Packt Publisher: English) - 2025

• Author of 'Structure and Principles of Arm Architecture for System Software Development' ( 2024, Korean Academy of Sciences Outstanding Book Award )

• Author of 'Learning the Structure and Principles of the Linux Kernel through Debugging' ( 2021, Korean Academy of Sciences Outstanding Book Award )

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Conference (KCC2022) - Tutorial presentation [Conquering the Linux Kernel using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor ( including domestic and overseas developers ) - (2020~2024)