As a current developer, this is a helpful lecture that covers only the essential points and is an excellent course. The process of being able to practice the content that is essential to know in order to reach the ranks of experts through trace32 is difficult to find worldwide, and it was very helpful.

mikeseohyungjin5975

Explains the core concepts and practical tips of RISC-V, the latest open-source based CPU architecture, simply and in detail.

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Learning RISC-V Architecture Through Debugging - Part 2

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입문

초급

중급이상

cpu-architecture

riscv

Course Introduction

Exception

RISC-V 예외 소개

Synchronous exception operation method

Exception Model (Detailed Execution Flow)

Exceptions and Software Stack

Exception Debugging Practice Part.1 (TRACE32)

Exception Debugging Practice Part.2 (TRACE32) - 1st Kernel Memory Dump Analysis

Exception Debugging Practice Part.3 (TRACE32) - Second Kernel Memory Dump Analysis

IRQ Exception

Introduction to Interrupt Controllers

RISC-V: Structure of Interrupt Controller

PLIC Operating Principle

Introduction to Calling Conventions

Calling Convention - Assembly Instructions

Key Stack Issue Case Study

Optimization strategies utilizing Calling Convention

Calling convention debugging practice Part.1 (TRACE32)

Calling convention debugging practice Part.2 - Stack corruption (TRACE32) - 3rd kernel memory dump analysis

Calling convention debugging practice Part.3 - Stack Overflow (TRACE32) - 4th kernel memory dump analysis

Memory dump extracted from RISC-V board (practice material)