Learning RISC-V Architecture Through Debugging - Part 2

<Notice>

1. To celebrate the launch of the first RISC-V course in Korea, a 30% discount coupon is being issued (first 100 people).

Coupon Link: https://inf.run/C7qRb

2. 2025 Latest Lecture Renewal

I have added the following lectures by discovering the features of the latest RISC-V architecture and useful content that can be immediately applied to practical projects.

• Added 'Synchronous Exception Operation Mechanism' session (4 lectures) - 07/23 (2025)

In the latest system software industry,
the emerging RISC-V architecture đang nổi lên

Recently, the open-source-based CPU architecture, RISC-V, has been emerging. You can easily find content like the following in IT-related media articles and news:

• Big tech companies such as nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startups in Korea designing various chips using RISC-V is increasing, and the proportion of products being developed based on RISC-V devices is rising.

• When designing AI semiconductors, the RISC-V-based CPU architecture is widely utilized.

• It is projected that 15 billion RISC-V-based devices will be released by 2026.

• In graduate schools (processor design), various research projects are being conducted using toolkits capable of designing RISC-V CPUs.

Embedded and system software companies are increasingly utilizing the RISC-V CPU architecture to develop their products. As a result, job seekers now need to prepare for RISC-V even during technical interviews.

Background of creating this course

From a beginner's perspective, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what is important among the vast amount of content that makes up RISC-V.

• I don't know which features among the contents of RISC-V are actually utilized in real-world projects.

• No matter how hard you read the RISC-V specification documents, it is difficult to understand them immediately.

  
  

• It is difficult to understand what the terms used to explain RISC-V actually mean.

  
  

Compared to the Arm architecture, there is a lack of materials related to the RISC-V architecture, and the reality is that there are insufficient resources that explain RISC-V in a specific and easy-to-understand manner. I created this course to help system software developers, including junior developers, overcome the difficulties they face while learning RISC-V.

Course structure and roadmap for Part 1 and Part 3

This lecture covers the content of Part 2, which focuses on the core features of RISC-V, out of the entire RISC-V lecture series.

• Part 1: Introduction to RISC-V, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture through Debugging Part 1)

• Part 2: Exception (Memory Abort Exception), Interrupt, PLIC (Platform-level Interrupt Controller), Calling convention

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension (Learning RISC-V Architecture Through Debugging Part 3)

  
  

The full RISC-V architecture course can be found in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key differentiating points of the lecture

What you will learn 📕

We explain the basic concepts of exceptions in detail and provide an easy-to-understand explanation of the core exception features defined in the RISC-V architecture.

Explains the execution flow of exceptions, a core feature of the RISC-V architecture. It also provides a detailed explanation of how exceptions are handled in a system composed of Machine mode and User mode.

It explains the exception codes defined in the RISC-V architecture that indicate the cause of an exception, and also describes the execution flow of how exceptions are handled via memory aborts.

It explains in detail the execution flow when exceptions and crashes are triggered from a software development perspective.

We will analyze the assembly instructions line by line to explain the flow of how an exception is triggered. Additionally, we will explain how the stack handles the process once an exception occurs.

We will practice exceptions by executing assembly instructions using the T32 debugging practice program. We will explain in detail which CSR (scause, mcause) registers change when an exception is triggered.

While practicing inducing exceptions with the TRACE32 program, we will explain in detail the exception handlers processed within the Linux kernel.

While analyzing a memory dump received from a RISC-V based board, I explain the operation of exceptions in the RISC-V architecture: analyzing kernel logs and analyzing the call stack.

We will conduct a debugging practice session on page tables using the TRACE32 program. Through this, we will identify the specific causes that triggered the exception.

Explains the basic operation of the interrupt controller defined in the RISC-V architecture. It provides easy-to-understand explanations of the structures of PLIC and CLIC.

We will review the exception codes related to interrupts and explain the structure of the PLIC (Platform Level Interrupt Controller).

I will explain the core hardware components that make up the PLIC and provide an easy-to-understand explanation of the CSR registers that control the PLIC.

Explains the Calling Convention introduced in the RISC-V architecture and reviews the registers that support the Calling Convention.

I will explain the big picture of how arguments passed to functions are handled.

Analyze the assembly instructions that support the Calling Convention of the RISC-V architecture. Additionally, analyze example assembly instructions - analysis of the c.sdsp instruction.

Analyze assembly instructions that support the Calling Convention of the RISC-V architecture. Additionally, analyze example assembly instructions - Analysis of the c.ldsp instruction

Analyze assembly instructions that support the calling convention of the RISC-V architecture. Additionally, analyze example assembly instructions - Analysis of the c.ldsp instruction.

We will conduct a TRACE32 debugging practice session on restoring a corrupted call stack.

Through TRACE32 debugging practice, we analyze memory dumps caused by stack overflows.

Based on my experience in book writing and lecturing,
deeper and more detailed than anyone else!

In the domestic system software field, I am the unprecedented! author who wrote books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books were selected as Excellent Academic Books by the National Academy of Sciences of the Republic of Korea), and I am a first in Korea to become a "Reverse Engineering Armv8-A Systems" (English) global author through an overseas publisher (Packt). Above all, I am an active developer who is most well-versed in the latest system software trends (Electric Vehicles, System Semiconductors - System Software). I am also an educator who is most actively engaged in spreading knowledge in the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' Author of the book (English), (Packt Publishing), (Nhà xuất bản Packt)

• Author of 'The Structure and Principles of Arm Architecture for System Software Development' (2024, National Academy of Sciences Outstanding Scholarly Book Award)

• Author of 'Structure and Principles of the Linux Kernel Learned Through Debugging' (2021, National Academy of Sciences Outstanding Scholarly Book Award))

• Main Instructor for 'Programmers Dev Course: Linux System and Kernel Expert'

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' internal instructor (including domestic and overseas developers) - (2020~2024)