Verilog FPGA Program 5 (Serdes)

FPGA Design Taught by an Expert with Over 20 Years of Experience 📑

Verilog HDL is an FPGA programming language. It can be used to create not only FPGAs but also ASICs. There are many developers who are interested in Verilog or wish to level up their skills in the field.

However, Verilog and FPGA are very specialized fields, so it is extremely difficult to find lectures that provide detailed explanations. Although FPGA manufacturers provide documentation, there are so many documents and they are all in English, making it impossible to know which ones to even look at.

I have worked as a developer in the field for over 20 years and currently run a one-person business. I created this lecture because I wanted to pass on the knowledge I have accumulated to those working as developers or those preparing to become one.

The course consists of a total of 5 lectures.

This is the fifth lecture, focusing on LVDS (Serdes). LVDS is used for low-voltage, high-speed serial communication. FPGAs support Serdes to enable the implementation of LVDS. We will understand LVDS, generate Serdes, and comprehend its operation through simulation. Finally, we will implement LVDS transmission and reception and verify the operation on a development board (HIL-A35T).

If there are any parts of the lecture you do not understand, please post your questions through the Inflearn community or the cafe I operate, and I will provide you with answers.

💾 Please check before taking the course!

• This course is a text-based lecture in electronic document format. All source files explained in the lecture are provided to those who take the course. The lecture is planned to be produced as a video in the future.

• The tool used in this lecture is Vivado 2018.3.

• The board used for the practice in this lecture is the HIL-A35T developed by our company specifically for the course. It can be purchased at our official Smart Store (Smart Store link: https://smartstore.naver.com/ihil)

• Lecture materials can be downloaded from 'Section 0 - Material Sharing Link - Attachment'.

Course Features ✨

Everything about LVDS communication is included

There are very few documents that cover implementing LVDS on FPGAs. In fact, while Xilinx provides a wealth of documentation, the sheer volume and the fact that they are in English make it very difficult to know which documents to reference.

This course covers everything about LVDS. It includes an explanation of LVDS, creating Serdes, understanding its operation through simulation, and ultimately implementing LVDS transmission and reception by downloading it to a target board. Through this process, you will understand everything about LVDS and be able to apply it in the field.

Try upgrading your Verilog skills

LVDS is an excellent skill for those who want to learn Verilog. Even many people with extensive development experience have not had the chance to work with LVDS. We provide you with the opportunity to take your Verilog skills to the next level.

Practical, industry-applicable source code is provided

For those who purchase this course, all source codes explained in the lectures will be provided. The provided sources consist of materials that were coded from scratch and verified one by one during the production of the course. Furthermore, they are composed of codes that can be used immediately in the field. We hope you become a master of LVDS through this course.

📢 The course consists of a total of 5 lectures. This is Lecture 5.

Lecture 1: Verilog FPGA Program 1

• Implementation of Basic Functions

Lecture 2: Verilog FPGA Program 2

• Microblaze

Lecture 3: Verilog FPGA Program 3

• DDR Controller

Lecture 4: Verilog FPGA Program 4

• MCU Porting

Lecture 5: Verilog FPGA Program 5

• LVDS / Serdes

  
  

Basics (Appendix): Basics of FPGA Utilization Using Verilog

📢 The lectures vary depending on the practice board. Please be careful when purchasing the course.

1. Arty A7-35T Board

   
   

   • Verilog FPGA Program 1 (Arty A7-35T)

   • Verilog FPGA Program 2 (MicroBlaze1, Arty A7-35T)

   • Verilog FPGA Program 2 (MicroBlaze2, Arty A7-35T)

   • Verilog FPGA Program 3 (DDR Controller, Arty A7-35T)

   • Verilog FPGA Program 4 (MCU Porting, Arty A7-35T)

2. Zynq mini 7020 board

   • Verilog FPGA Program 1 (Zynq mini 7020)

   • Verilog ZYNQ Program1 (Zynq mini 7020)

3. HIL-A35T Board (Developed in-house for the lecture)

   • Verilog FPGA Program 1 (HIL-A35T)

   • Verilog FPGA Program 2 (MicroBlaze, HIL-A35T)

     
     

   • Verilog FPGA Program 3 (DDR Controller, HIL-A35T)

   • Verilog FPGA Program 4 (MCU Porting, HIL-A35T)

   • Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T)

Detailed Curriculum 📚

Section 1. HW Configuration

• Explaining the development board (HIL-A35T).

Section 2. LVDS Review

• Understand the contents of LVDS.

• Explains important details about Serdes (ISERDESE2, OSERDESE2).

Section 3. LVDS Implementation

• Create the Serdes IP and understand its operation through simulation.

• Implement the LVDS transmission and reception code, and verify it through simulation.

• Download the results to the target board and verify the results.

Section 4. 2-Lane, 4-Lane Implementation

• Explain how to expand the lanes and verify the results on the board.

  
  

Section 5. Implementing Maximum Transfer Speed

• Explain how to implement the maximum transmission speed and verify the results on the board.

Section 6. Implementing LVDS Reception Without Using Serdes

• Implement LVDS reception without using Serdes IP.