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High-Speed Embedded Board Design Project (feat. Smartphone)

This is a practical AP-based high-speed motherboard design course required by professionals at Samsung, LG, Hyundai Motor, and Hanwha Systems in the robotics and industrial equipment sectors. Based on the RK3399 SOM, the course covers PMIC power sequencing, LPDDR4 constraints (length/impedance/return path), and the design of USB3, HDMI, MIPI, and PCIe all in one package. You will complete the process from design rationale documentation and schematic creation to layout design and bring-up inspection as final deliverables.

12 learners are taking this course

Level Intermediate

Course period Unlimited

Embedded
Embedded
hardware
hardware
artwork
artwork
kicad
kicad
orcad
orcad
Embedded
Embedded
hardware
hardware
artwork
artwork
kicad
kicad
orcad
orcad

What you will gain after the course

  • Creating a portfolio for AP-level motherboard design experience, going beyond the 'MCU board' level.

  • Establishment of high-speed interface (PCIe, DDR, USB/HDMI/MIPI, etc.) design checklists and summary of failure causes and prevention points

  • Organize DDR/High-speed signal design constraints (length, impedance, group criteria) and complete the Constraint Table.

  • Documenting power supply (PMIC/sequencing/PDN) design rationale (rail definition, load, decoupling) and creating design criteria tables.

  • Define stack-up/layout priorities (DDR → High-speed I/O → Others) and document routing strategies.

  • Organize the bring-up inspection sequence (Power → Clock → Boot → DDR → I/O) and create a hardware verification flow.

"Smartphone SoC" level
For those who want to do circuit design,
please pay attention 👇

🔎If you look at job postings from major corporations...

Samsung Electronics MX, DA, VD Divisions, LG Electronics, Hyundai Motor Company/Hyundai Mobis, Hanwha Systems, etc.

What is the "circuit design and HW design competency" required by all industries?

Samsung Electronics DX Division MX Business Unit Circuit Design Experienced Recruitment Job Description

It is precisely the "High-speed design" competency.


If you think about it,
all the electronic devices we use
often exceed 100Mbps or even 1Gbps,
such as PCIe, DDR, USB4/Thunderbolt, Ethernet, and HDMI.

Various electronic products equipped with High-speed Systems


However, while we may have
"STM32 embedded board design experience" (Link),
we lack experience in designing
"High-speed Boards" based on AP-level "SoC (System on Chip)."

Various types of SoC and SOM-based high-speed boards


These "SoC boards" have as many as
PCB Layers ranging from 10 to 14 layers, making it nearly
"impossible" to learn on your own.

PCB Stack with 10~14 Layers

🔥We will help you master SoC-based high-speed circuit design in one go.

AP (SoC) Class
Mainboard
Schematic Design

This course covers the practical schematic design of an RK3399 SOM-based AP (SoC) board.
Focusing on Power Tree/Power Sequencing, LPDDR4·eMMC·WiFi circuit configuration, and USB3/HDMI/MIPI/PCIe interface design points, you can learn everything from the actual design flow to documentation methods.

AP(SoC)-level Mainboard Schematic Design

High-speed
PCB Layout production and
Gerber generation

You will practice the entire PCB layout process, from defining stackup and impedance to placement, routing, and high-speed interface (DDR/USB3/PCIe/HDMI/MIPI, etc.) routing and length matching. Finally, you will perform DRC/DFM reviews and generate manufacturing outputs such as Gerber and drill files, completing the process with a production-ready result.

High-speed PCB Layout Creation and Gerber Generation

12-Layer Stackup
High-Speed
Board Design

Design a 12-layer stackup configuration tailored for an RK3399 AP-class board and optimize the layers based on reference plane/return path standards for high-speed signals. Additionally, consult with the PCB manufacturer regarding impedance tolerance, materials (prepreg/copper foil), via structures, and process limits using a checklist to finalize a manufacturable stackup.

12-Layer Stackup High-Speed Board Design

3D View-based
Layout Verification and
Portfolio Generation

Using the KiCad tool's 3D View, you will visually verify board geometry, connector interference, and component heights to improve layout quality. The practical results are organized into 3D rendered images and verification evidence (checklists), which can be used as a portfolio to prove your design capabilities in resumes, cover letters, and interviews.

3D View-based Layout Verification and Portfolio Production

Self-study notes provided

There are topics that could not be covered during the 20-hour lecture due to time constraints. Therefore, I have compiled practical know-how from field engineers, debugging case studies, common power sequencing/Power Tree improvement points encountered during practice, LPDDR4 constraints and length matching troubleshooting, high-speed routing error cases, and even checklists for DFM/Gerber generation into a separate self-study note. You can refer to it immediately whenever you get stuck while reviewing or working on assignments.

Self-study notes included


📚

Practical project-based
design capability enhancement!

Embedded Board Design Overview and Career Roadmap

Section 1

Embedded Board Design Overview and Career Roadmap

In this section, we will explore the overall flow of embedded board design, focusing on the RK3399 SOM board design. We will compare the differences with STM32 boards, link the learning content through relevant job description keywords, and clearly define the roles between circuit design, HW design, and embedded design.


Establishing PCB HW Design Tool Environment (Schematic)

Section 2

Establishing the PCB HW Design Tool Environment (Schematic)

Set up the KiCad or OrCAD environment, which are essential tools for PCB design, and learn how to create component libraries and symbols for embedded board design. Additionally, cover power tree design, including LDO/DCDC decoupling strategies, and JTAG/SWD debugging interface configuration.


Establishing PCB HW Design Tool Environment (Layout)

Section 3

PCB HW Design Tool Environment Setup (Layout)

In this section, we optimize signal, power, and ground planes through 4-layer PCB stack-up design. You will learn the process of migrating schematic data to the PCB and component placement strategies, followed by hands-on layout practice for Ethernet PHY and MCU-based blocks.


Processor Selection and Understanding RK3399

Section 4

Processor Selection and Understanding RK3399

Learn about the various types of processor packages (SoC, SOM) and their selection criteria, and derive core, clock, and interface specifications based on a requirement sheet. Analyze the key contents of the RK3399 datasheet, and understand the differences between DDRx and LPDDRx interface concepts and their application methods.


LPDDR4 Interface Structure and Design Strategy

Section 5

LPDDR4 Interface Structure and Design Strategy

Compare the selection criteria between DDR3/DDR4 and LPDDR3/LPDDR4, and conduct an in-depth analysis of LPDDR4's data, address/command, control, and clock group structures. Understand DDR layout topologies and the concept of data skew, and study DDR-related content through the RK3399 datasheet.


LPDDR4 SDRAM Selection and Schematic Design

Section 6

LPDDR4 SDRAM Selection and Schematic Design

We select the optimal LPDDR4 SDRAM by comparing and analyzing the specifications, unit prices, and lead times of various SDRAM vendors. Based on JEDEC standard documents, we study the core details of the RS512M32LZ4D2ANP LPDDR4 and proceed with detailed schematic design practice, including basic connection structures, option pins, termination, and pull-up processing.


eMMC and WIFI Storage/Wireless Module Design

Section 7

eMMC and WIFI Storage/Wireless Module Design

Understand the eMMC 5.1 standard and select the optimal storage solution by comparing and analyzing the performance, lifespan, and cost of different NAND eMMC types. Proceed with schematic design based on the KLMAG1JETD-B041 eMMC datasheet, and learn the selection criteria for WLAN/WIFI modules as well as pin configuration, power supply, and condition setting methods for SDMMC-based WIFI modules.


WIFI Module, Power Tree, DDR Controller Design

Section 8

WIFI Module, Power Tree, and DDR Controller Design

Learn the schematic design of the WIFI module and considerations for RF peripherals, and cover the design of major power rails such as VDD_GPU and VDD_BIGCPU. Master the key points of schematic design for the RK3399 LPDDR4 DDR controller, and engage in integrated practical training for the WIFI module, power pins, and SDRAM schematic design.


RK3399 Symbol Partitioning and Library Configuration

Section 9

RK3399 Symbol Partitioning and Library Configuration

You will learn how to split symbols for various interfaces of the RK3399, including the power supply unit, DDR controller, PCIe, ADC, HDMI, MIPI DSI, and MIPI CSI. Through this, you will establish library configuration strategies for efficient schematic design and perform a comparative review of the RK3399 Schematic Design Guide.


Essential Hardware Interface Summary

Section 10

Essential Hardware Interface Summary

Learn the operating principles and board design application patterns of I2C, SPI, UART, LVDS, I2S, SDIO, and Ethernet interfaces (MII, RMII, GMII, RGMII). Additionally, understand the overall structure of essential interfaces such as USB, Type-C, CAMIF, eDP, and HDMI, and conduct practical schematic design exercises.


PMIC, Ethernet PHY, Stackup Design

Section 11

PMIC, Ethernet PHY, Stackup Design

Organize the power rail structure based on the RK3399 PMU system block and learn the selection criteria for the RK808 PMIC and how to create a Pugh matrix. Conduct hands-on schematic design for the PMIC, Buck Converter, and Ethernet PHY, and cover 4/6/8/12-layer stackup design along with key points for manufacturer consultation.


12-layer SOM Board Initial Placement Plan

Section 12

12-layer SOM Board Initial Placement Plan

We will configure a 12-layer stackup optimized for SOM boards, import the DXF board outline, and prepare for component placement. We will establish a SOM board placement strategy centered on the SoC, memory, and connectors, and review a checklist of items to verify after the initial placement.


Advanced Component Placement and DFM Perspectives

Section 13

Advanced Component Placement and DFM Perspectives

Check the component placement quality, summarize improvement points, and learn placement guides considering assembly, heat dissipation, and serviceability. Organize placement rules with mass production in mind and improve placement quality through hands-on practice.


RK3399 Fanout and Design Rule

Section 14

RK3399 Fanout and Design Rule

Learn how to set design rules such as vias, clearances, and track widths, and examine RK3399 BGA power fanout strategies and pattern examples. Master the methods for defining 50Ω and 90Ω impedance profiles and linking them with the stackup, and conduct layout practice considering fanout.


LPDDR4 Byte Group Layout

Section 15

LPDDR4 Byte Group Layout

Establish placement and layout plans for LPDDR4 byte groups, and organize byte group fanout and routing rules in detail. Conduct LPDDR4 byte group layout practice and learn routing patterns for the remaining byte groups and high-speed signals.


High-speed Length Matching Workflow

Section 16

High-speed Length Matching Workflow

We will organize high-speed signal design rules and priorities, and learn how to select and group interfaces for length matching. You will understand the step-by-step procedure and checkpoints for length matching, and proceed with practical training through an LPDDR4 length matching demo and target value examples.


We can solve the concerns
of people like this!

📌

New/Junior engineers
with limited circuit design experience

  • Those who have experience in MCU board design but are concerned about their job competitiveness due to a lack of an AP-level high-speed board design portfolio.

  • Those who want to systematically build experience in AP-based high-speed design required in the field

📌

Electronic engineering majors
seeking a gradual career change

  • Those who feel career anxiety due to the decrease in semiconductor IC design job openings, but want to create a new career Plan B through board-level design.

  • Those who want to increase their competitiveness by concretizing their AP-level motherboard design capabilities

📌

Current professionals who have difficulty
explaining design rationale

  • Those who always get stuck in interviews because they only talk about circuit/layout experience and are weak at providing specific design reasons or rationales.

  • Those who want to learn how to document design rationales and package their portfolio based on practical experience to utilize in career moves or negotiations.

Notes before taking the course


Practice Environment

  • Operating System: Windows 10/11 (64-bit)

  • Required Software: KiCad (Free)


    Download → https://www.kicad.org/download/windows
    (OrCAD / Altium can be used and is compatible)

  • Recommended Specifications: 8GB RAM or more, 10GB or more SSD storage space, Intel i5-level CPU or higher

Prerequisite Knowledge and Precautions

  • Experience in MCU board design and basic knowledge of circuit design required
    Prerequisite course → https://inf.run/z6KM1

  • Essential to understand the basic principles of Schematic diagrams and PCB layout

  • AP-level board design is much more difficult than MCU boards, so a learning attitude of
    studying and researching on your own is important!!

Learning Materials

  • Lecture slide PDFs provided

  • Datasheets and related documents for the RK3399 SOM and devices used in the practice sessions are provided.

  • Feedback provided upon assignment completion and submission
    Feedback will be shared via the Naver Cafe → https://cafe.naver.com/samcoach

  • Provision of design rationale documents, schematics, and layout example files


✨✨✨✨✨✨✨✨✨✨✨✨✨✨

1st Early Bird Discount EVENT !

1st Early Bird EVENT : 600,000 KRW X → 390,000 KRW

2nd Early Bird EVENT: 600,000 KRW X → 420,000 KRW

3rd Early Bird EVENT: 600,000 KRW X → 450,000 KRW

...
✨✨✨✨✨✨✨✨✨✨✨✨✨✨

This is a course where I communicate with students through the Naver Cafe!

  1. Please join the open KakaoTalk chat room for announcements! (Participation code: 0459)
    https://open.kakao.com/o/gm1KFaCg

  2. Please join the Naver Cafe to receive the student materials!


    https://cafe.naver.com/samcoach

  3. Through live classes held every month, we provide assignment feedback and counseling for your concerns!


    ➡ Schedule and live class details are announced every month via the Naver Cafe (Replays provided!)

  4. We provide a variety of information and events for your job search!
    ➡ Cafe level-up + continuous updates + accessible even after completion.

Access to Sam Coach's community and EVENTs for circuit design job seekers is now ON!

We invite you to Samcoach's Naver Cafe for job seekers in circuit design!

https://cafe.naver.com/samcoach
To upgrade your cafe membership level, please apply for the lecture, join the cafe, and then fill out the form below!
https://forms.gle/r76HSgCHNyf43qmV6

For students,

  • Samcoach Group Consulting Pass

  • Advanced Student Resource Access

  • Discounts on other content

Various benefits such as these are prepared for you.

Sam-Coach Naver Cafe

Continuous updates planned!

I plan to continuously communicate with students and provide updates on content that requires supplementation.


Nice to meet you, I'm Sam Coach, your circuit design mentor! 🙌

  • Former Samsung Electronics DS Division / 5th-year Chip Circuit Design Engineer

    • Analog IP / Digital Scenario Design

    • Class A patent application filed

  • Technical support for global foreign company engineers

  • Former) Startup Hardware Accelerator / MCU Firmware Design

  • Former) Major Home Appliance Company / All-in-one Water Purifier Production Technology

  • Former) Mid-sized medical device company / PCB HW, CIS, DDI ASIC design


🧭 Mentor Activities

  • Author of the Circuit Design part of 'The Semiconductor Job Bible: Insights from Current Professionals in Each Role'

  • 'Korea Semiconductor Industry Association SEMI-MOOC' Circuit Design Core Theory and Simulation Instructor

  • Circuit Design Job Mentor at 'LetUin (No. 1 in STEM Employment) & Career Community Comento'

  • Conducted circuit design job boot camps and special lectures at more than 10 universities, including Yonsei University, Hanyang University, and Konkuk University.

  • Over 200 sessions of resume, cover letter, and interview consulting for circuit design roles

  • 'K-Digital Basic Competency Training' Instructor (Stop with the difficult circuit formulas; semiconductor circuit (chip) design done with your eyes)

  • Operating the YouTube channel 'Coach Sam, the Pathfinder for Circuit Design Jobs'

I'll see you in the lecture! 🖐🏻

The fact that you are reading this right now means you are more than qualified to take on the challenge of a circuit design role. My role is to help the efforts of those passionate about circuits lead all the way to a successful job offer.
This lecture will gift those of you challenging circuit design with a "distinctive design experience."

Of course, it would be great if we could work together on circuit design projects following the roadmap, but I recommend you first try what you can do on your own through the free lecture (click). Then, if you feel the need, please sign up for the course.

I look forward to seeing you in the lecture. Thank you 😊

🪜 View Coach Sam's Full Circuit Design Lecture Roadmap
(Click the image below)


Recommended for
these people

Who is this course right for?

  • Job seekers who have experience with undergraduate projects or MCU boards but lack experience with AP-level boards, making it difficult to differentiate their portfolios.

  • An electronics engineering major who feels uncertain about their career path due to the decrease in semiconductor IC design job openings and wants to solidify a Plan B in board-level design.

  • Those who always get stuck in interviews because they only say "I did the schematic/layout" and provide weak explanations for why they made those specific design choices.

  • Those who find DDR/high-speed interfaces difficult and lack clear standards for setting constraints (length, impedance, return path).

  • Current professionals who have experience with power (PMIC/sequencing/PDN) but lack experience in AP, DDR, and high-speed I/O integration, and thus need a 'main project' to increase their market value.

  • An engineer whose career has stagnated because they only handle MCU and power-related tasks at work, while high-speed boards are always assigned to other teams.

  • Those who want to systematize inspection sequences and observation points because they currently rely on intuition when problems occur during bring-up.

  • Those who want to create a compelling one-liner for job changes or negotiations and need methods for documenting design rationale and packaging their portfolio.

Need to know before starting?

  • Basic knowledge of electronic circuits (Power/Capacitor/Regulator, basic concepts of digital signals)

  • Reading comprehension skills at a level that allows you to read datasheets and reference designs to extract key requirements (even if it's your first time, the lecture will provide the standards).

  • A PC capable of installing and running KiCad or Altium (Instructions on how to use the tools will be covered in the 'Practice Videos')

  • PC for practice: Windows recommended (Specifications capable of EDA tool installation, library management, and output file generation)

  • (Recommended) Basic understanding of the PCB fabrication/assembly flow (Guidance on Gerber/BoM/Pick-and-Place, etc., from a deliverables perspective)

Hello
This is samcoach

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Experience & Background

Current) Major Semiconductor Company (Chip Circuit Design, 4th Year)

  • Analog IP / Digital Scenario Design

  • Class A Patent Application

  • Technical support for global foreign company engineers

Former) Startup Incubator (MCU Firmware Design)

Former) Major Corporation Home Appliance Company (All-in-one Water Purifier Production Technology)

Former) Mid-sized medical device company (CIS, DDI ASIC design)

Yes, Former) Startup Incubating Company (MCU Firmware Design) Former) Large Enterprise Home Appliance Company (All-in-one Water Purifier Production Technology) Former) Mid-sized Medical Device Company (CIS, DDI ASIC Design)

Yes, Former) Startup Incubating Company (MCU Firmware Design) Former) Large Enterprise Home Appliance Company (All-in-one Water Purifier Production Technology) Former) Mid-sized Medical Device Company (CIS, DDI ASIC Design)

You can definitely take on the challenge of getting a job or changing careers in CHIP design.

Get one step closer to landing a job or switching careers in CHIP design with me!

"Are you dreaming of a career in semiconductor analog/digital circuit design?

I will help you from the basics through the eyes of a current employee at S Electronics, a major corporation!

Get closer to landing a job or switching careers in CHIP design! "Are you dreaming of a career in semiconductor analog/digital circuit design? I will help you from the basics through the eyes of a current employee at S Electronics, a major corporation!"

Nice to meet you! I am Coach Sam, currently designing system semiconductors at S Electronics :)

"Do you dream of becoming a circuit designer? I will help you from the basics through the eyes of a current employee at S Electronics, a major corporation!" Nice to meet you! I am Sam-coach, currently designing system semiconductors at S Electronics. :)

I have gone through many trials and errors while taking on the challenge of circuit design, starting from a startup.

I gained experience in PCB design, F/W design, FPGA design, and CHIP design through trial and error.

However, there was one thing I found disappointing.

I've faced many trials and errors while taking on these challenges. I gained experience in PCB design, F/W design, FPGA design, and CHIP design in a somewhat haphazard way. However, I always felt that something was missing.

'Why are there so few opportunities for systematic hands-on practice and information about employment in the field of circuit design?'

I experienced chip design in a haphazard, trial-and-error way. However, I felt one lingering regret: "Why are there so few structured hands-on opportunities and job-related information in the field of circuit design?"

While there was plenty of content for fields like semiconductor processing and programming, circuit design felt like a "hidden world" because information was so scarce.

Those of you preparing for a career in circuit design who are reading this have likely felt the same frustration I did. That's why I interviewed professionals in the field, asked my professors, and took IDEC courses.

Those of you preparing for a career in circuit design who are reading this have likely felt the same sense of frustration that I did.

So, you might try interviewing current professionals in the field, asking your professors for advice, or taking IDEC courses.

However, in most cases, you still find yourself feeling like you almost get it, but not quite.

SO! I went ahead and created a structured course myself that leads directly to employment!

I have experienced everything from [Analog Circuits -> Digital Systems -> MCU Firmware -> Driver Design -> Software], and

Through 'Top-down / Bottom-up' skills, I have become able to perfectly explain products and circuits.

And through my practical circuit courses on Inflearn, I will share everything from my own intuitive methods for interpreting 'analog/digital circuits' to the ways I evaluate trade-offs.

And on Inflearn, as we work with practical circuits, I plan to share everything from my own intuitive methods for interpreting 'analog/digital circuits' to the ways of evaluating trade-offs.

Let's build a solid foundation together, develop practical skills, and create your very own chip design story!

Let's build a solid foundation together, develop practical skills, and create your own unique chip design story!

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105 lectures ∙ (23hr 6min)

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