Learning RISC-V Architecture Through Debugging - Part 3

In the modern systems software industry
The Emerging RISC-V Architecture

Recently, the RISC-V architecture, an open source-based CPU architecture, is on the rise. If you look at IT-related media articles or news, you can immediately see the following:

• Big tech companies like nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startup companies designing various chips using RISC-V in Korea is increasing, and the proportion of products developed based on RISC-V devices is increasing.

• When designing AI semiconductors, RISC-V-based CPU architecture is widely used.

• 15 billion devices are expected to be RISC-V-based by 2026.

• In the graduate school (processor design), various studies are being conducted using a toolkit that can design RISC-V CPUs.

Embedded and system software companies are increasingly developing products using RISC-V CPU architectures, so job seekers need to prepare for RISC-V during technical interviews.

Background on creating the lecture

For beginners, the RISC-V architecture is difficult to learn. Here are some reasons why:

• I don't know what is important among the vast content that makes up RISC-V.

• I don't know which functions of RISC-V are used in real projects.

• No matter how hard you read the RISC-V specification document, it is difficult to understand it right away.

  
  

• It is difficult to know what the term itself that describes RISC-V means.

  
  

This lecture is the third lecture in the series Learning RISC-V Architecture through Debugging , and covers the contents that will help you go beyond the beginner level and become a highly paid system software developer - explaining the memory system (virtual memory, memory barriers, cache) and Hypervisor Extension functions.

Lecture structure and roadmap for parts 2 and 3

This lecture covers the contents of Part 3, which is the core function of RISC-V, among the entire list of RISC-V lectures.

• Part 1: Introduction to RISC-V, Registers, Assembly Instructions, Privilege Mode ( Learning RISC-V Architecture through Debugging Part 1 )

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling convention ( Learning RISC-V Architecture through Debugging Part 2 )

• Part 3: Virtual Memory System, Cache, Fences/Barriers, Hypervisor Extension

  
  

The full RISC-V architecture lecture can be found in the Roadmap - ' RISC-V Architecture for System Software Developers ' lecture.

Key differentiating points of the lecture

Learn about these things 📕

Introduces the main memory features of the RISC-V architecture, and also introduces the core functions that make up the virtual memory system. Explained in an easy-to-understand manner with a big picture.

Introduces the virtual memory map, which is the core of the virtual memory system. It also provides an easy-to-understand explanation of the range of virtual addresses for kernel space and user space.

Describes the satp register that sets up the page table, and explains the concept of virtual addresses in an easy-to-understand way through memory dump debugging practice. (Memory dumps are provided in the lecture materials.)

Explains the concepts of virtual addresses and page tables, and explains the scope of virtual addresses through a real case study.

Describes the structure of a multi-level page table and explains the Page Table Entry (PTE) in detail.

We will explain in detail the process of directly converting virtual addresses into physical addresses through multi-level page tables. We will also practice debugging by converting virtual addresses into physical addresses using the Crash Utility program.

By analyzing the MMU specifications of SiFive's U74 core and P550 core, we explain in detail how the MMU works from a hardware design perspective.

Explains memory reordering and explains in an easy-to-understand way how the fence command works to prevent memory reordering.

Describes the basic structure (form) of the fence command and explains in detail how the fence command works with various options applied.

Explains how the fence command works in a multi-core system environment - Analyzes how the fence command synchronizes with other cores when executed. Also explains the fence command while analyzing example assembly instructions.

We introduce the fence.i command and explain the big picture of the process flow when the fence.i command is executed.

We analyze the fence.i instruction by analyzing various example assembly routines. We analyze the fence.i instruction by comparing it to the Arm architecture.

Explains the basic concepts of caching and why caching is used.

We explain how caches work in multi-core systems and analyze the key features of caches defined in RISC-V, while comparing them to the Arm architecture.

Describes the basic components that make up a cache, and details how addresses are handled during a cache lookup.

We introduce the hypervisor and describe the privileged mode in which the hypervisor runs on the RISC-V architecture.

Introduces the core features of the Hypervisor Extension defined in the RISC-V architecture and explains how to enable the Hypervisor Extension.

Describes the execution flow in which the Hypervisor first controls an exception when it occurs in the Guest OS.

Based on my experience writing books and giving lectures
More in-depth and detailed than anyone else!

Unparalleled in the domestic system software field! Author of 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' ( both books selected as excellent books by the Korean Academy of Sciences ) and global author who wrote the book "Reverse Engineering Armv8-A Systems" (English) through a foreign publisher (Packt) for the first time in Korea . Above all, he is a working developer who knows the latest system software trends (electric vehicles, system semiconductors - system software) the best. He is also an educator who is most active in knowledge dissemination in the field of system software.

• Author of the book 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' (Packt Publishers)

• Author of 'Structure and Principles of Arm Architecture for System Software Development' ( 2024, Korean Academy of Sciences Outstanding Book Award )

• Author of 'Learning the Structure and Principles of the Linux Kernel through Debugging' ( 2021, Korean Academy of Sciences Outstanding Book Award )

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Conference (KCC2022) - Tutorial presentation [Conquering the Linux Kernel using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor ( including domestic and overseas developers ) - (2020~2024)