inflearn logo
강의

Course

Instructor
inflearn logo
Challenge
Recruiting
Hardware

/

Semiconductor

[2-Week Synthesis Practice Challenge, Cohort 9] RTL Synthesis in a Real-World Environment (Synopsys Design Compiler)

Recruitment period: 2026-09-07 ~ 2026-09-21 Course period: 2026-09-22 ~ 2026-10-05 Content: Practice the process of converting RTL-level digital circuit design code described in HDL into logic gates

EDA
digital-logic
vlsi
soc
asic

17개 수업 학습

질문하고 즉시 답을 얻어요.

MetaEncore님과 함께해요!

Inflearn Verified

198

Learners

27

Reviews

36

Answers

4.7

Rating

12

Courses

Market demand for application-specific chips (ASICs, application-specific integrated circuits), such as AI (Artificial Intelligence) and IoT (Internet of Things), is growing, and although many chips are actually being designed, few lead to tangible changes in our daily lives.

Many ASIC designs contain functional errors or fail to meet their planned performance requirements. To create high-quality semiconductors that make our lives better, we need services that provide advanced functional and performance verification capable of handling increasingly large and complex designs. MetaEncore is a company dedicated to increasing the number of semiconductors that benefit people by providing such services.

More
인프런9기

*Please be sure to check the recruitment and course schedule.

*After applying for the course, completing the survey is required.

Please check!

  • This course includes a two-week license to use Synopsys toolsand focuses on how to use the tools.

  • Synopsys tools are generally only available to currently employed professionals, but

    For this challenge course, we provide students with the opportunity to try the tools themselves.


  • After applying, you must complete the survey to receive access to the tool.

[2-Week Synthesis Practice Challenge, Cohort 9]

Recruitment period: 2026-09-07 ~ 2026-09-21 5:00 PM

Course schedule: 2026-09-22 9:00 AM ~ 2026-10-05 5:00 PM

*The course schedule and the Design Compiler tool license period are the same.


Synthesis

What is synthesis?

  • Convert a Register Transfer Level design written in an HDL such as Verilog into the Gate Level.

  • During the conversion process, the design is optimized according to the constraints specified in the Synopsys Design Constraint.

  • Ultimately mapped to standard cells provided by the foundry


The Importance of Synthesis Experience

Create a compelling personal statement

The industry prefers entry-level employees with experience in synthesis and timing verification.
However, gaining experience in synthesis requires significant time and money.
Although the industry demands experience, offline training programs are also highly competitive.
This course provides a training environment that faithfully replicates the one used in real-world practice.
It uses Synopsys Design Compiler, the tool most widely used in the industry.
Through this course, you will be able to create a compelling personal statement that gives you a competitive edge when applying to offline training programs and in the job market.

Korea's first online synthesis hands-on course

What is Covered in the Synthesis Practice Course

  • Section 1. Preparing the Practice Environment


    • You can set up the practice environment within 5 minutes.

  • Section 2. Preparing the Practice Design

    • Practice how to load an RTL Design described by the provided HDL code into the Tool

    • Practice checking the imported RTL Design.

    • Methods for accessing each object hands-on exercise

  • Section 3. Synopsys Design Constraints Specification

    • Practice declaring clocks, the core of digital circuits

    • Practice: Modeling the External Environment of the Chip

    • Practice on basic timing verification variations and exceptions

  • Section 4.

    • Practice preparing for compilation to the gate level

    • Practice proceeding with compilation and comparison

    • Report Verification Practice After Compilation

What You Gain from the Synthesis Practice Course

  • Experience the environment used in practice and Design Compiler, the most widely used tool.

  • You can differentiate your personal statement while gaining a competitive edge.


Prerequisites

  • Because it is the process of mapping circuits designed in a language to Gates with a ‘physical’ form, the following prerequisite knowledge is required.

    • Digital Logic Circuits

    • CMOS operating principles

    • Basic knowledge of the Verilog language

    • [Inflearn Course] We recommend taking the Basic Design Synthesis Training course first.
      https://inf.run/XkbCP

  • Linux Environment

    • In practice, the Linux environment is used.

    • Unlike Windows, it primarily involves communicating with the computer by entering commands.

    • Knowing the main commands used in Linux is helpful.

  • TCL for communicating with EDA tools

    • It is an interpreted language, and most EDA tools operate through a TCL interface.


    • If you want to pursue a career in digital circuit design, it is a good idea to study it whenever you have the time.


Study reference site related to the lecture

9월

21일

챌린지 시작일

2026년 9월 21일 오후 03:00

챌린지 종료일

2026년 10월 5일 오전 08:00

챌린지 커리큘럼

All

17 lectures ∙ (3hr 7min)

Course Materials:

챌린지 전용 수업

챌린지에서 배워요

  • Gained hands-on experience in real-world environments, including Linux.

  • Experience with the synthesis tool most commonly used in practice

  • Create a distinctive and competitive personal statement with just one experience.

Recommended for
these people

Who is this course right for?

  • Those preparing for employment

  • Those looking to transition their work to semiconductor design implementation

Need to know before starting?

  • Fundamental Flow of Digital Circuit Design

  • Verilog HDL

  • Logic circuit

  • [Inflearn Course] Basic Design Synthesis Training (Digital Circuit Design Implementation)

취소 및 환불 규정
챌린지는 지식공유자가 설정한 수업 최소 정원이 충족되지 않을 경우, 폐강 안내가 고지되며 결제 내역이 자동취소됩니다.

MetaEncore's other courses

Check out other courses by the instructor!

Basic UVM Testbench (Circuit Design Verification)Course Thumbnail

Basic UVM Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, uvm

5.0

(5)

Mission
Mission

Through this course, you will understand the UVM Class library and learn testbench design techniques using UVM.

Basic

Basic

Verilog HDL, system-verilog, uvm

Basic UVM Testbench (Circuit Design Verification)Course Thumbnail

Basic UVM Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, uvm

5.0

(5)

Mission
Mission
Basic Design Synthesis Training (Digital Circuit Design Implementation)Course Thumbnail

Basic Design Synthesis Training (Digital Circuit Design Implementation)

MetaEncore

$254.10

Beginner / EDA, digital-logic, vlsi, soc, asic

5.0

(6)

Through what stages are semiconductor chips designed and manufactured? We will examine the basic concepts of logic circuits and the Chip Design Flow required for PI (Physical Implementation) / PD (Physical Design) roles step-by-step, and explore the key concepts of the synthesis process based on the tools used for digital chip circuit design in the industry.

Beginner

Beginner

EDA, digital-logic, vlsi

Basic Design Synthesis Training (Digital Circuit Design Implementation)Course Thumbnail

Basic Design Synthesis Training (Digital Circuit Design Implementation)

MetaEncore

$254.10

Beginner / EDA, digital-logic, vlsi, soc, asic

5.0

(6)

Basic SystemVerilog Testbench (Circuit Design Verification)Course Thumbnail

Basic SystemVerilog Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, verification, system-verilog-dpi

4.8

(14)

Mission
Mission

You will learn the basic syntax of SystemVerilog and testbench design techniques using SystemVerilog classes. Additionally, you can experience and learn the complete basic cycle of hardware circuit design verification by utilizing VCS, an EDA Tool from Synopsys used in the industry. Related search terms SystemVerilog, SystemVerilog, SystemVerilog, Verilog, Verilog, Verilog, SOC, circuit design, circuit verification, verification, Verification, chip design, chip verification, Samsung Electronics, Hynix, new employee training, in-house training, Synopsys, VCS, semiconductor, employment, career, fabless

Basic

Basic

Verilog HDL, system-verilog, verification

Basic SystemVerilog Testbench (Circuit Design Verification)Course Thumbnail

Basic SystemVerilog Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, verification, system-verilog-dpi

4.8

(14)

Mission
Mission

모집 인원 5명

$84.70