[2-Week Synthesis Practice Challenge 7th Batch] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

[2-Week Synthesis Practice Challenge 7th Cohort]

Recruitment Schedule: ~ 2026-06-15 5:00 PM

Lecture Schedule: 2026-06-16 9:00 AM ~ 2026-06-29 5:00 PM

*The lecture schedule and the Design Compiler Tool license period are the same.

Synthesis

What is Synthesis?

• Converting a Register Transfer Level design written in an HDL such as Verilog into a Gate Level design

• During the conversion process, the design is optimized according to constraints called Synopsys Design Constraints.

• Finally mapping to standard cells provided by the foundry

  
  

Importance of Synthesis Experience

Creating a Persuasive Self-Introduction Letter

The industry prefers new employees with experience in synthesis and timing verification.
However, gaining synthesis experience requires significant cost and time.
While the industry demands experience, offline training courses are also highly competitive.
This course provides an educational environment that replicates the actual settings used in the field.
It utilizes Synopsys Design Compiler, which is the most widely used tool in the industry.
Through this course, you will be able to create a competitive resume for offline training selection and the job market.

Korea's first online lecture for synthesis practice

What is covered in the synthesis practice lecture

• Section 1. Preparation of the Practice Environment

  
  

  • You can set up the practice environment in less than 5 minutes.

• Section 2. Preparation of Practice Design

  • Practice on how to read the RTL Design described in the provided HDL code into the tool

  • Practice the process of checking the loaded RTL design

  • Practice on methods for accessing each object

• Section 3. Describing Synopsys Design Constraints

  • Practice declaring the Clock, the core of digital circuits

  • Practice modeling the chip's external environment

  • Practice on basic timing verification transformations and exceptions

• Section 4.

  • Preparation practice for compiling to the Gate Level

  • Practice and comparison of the compilation process

  • Practice on reports that must be checked after compilation

What you will gain from the synthesis practice lecture

• You will experience the environment used in practice and the most widely used Design Compiler.

• You can differentiate your self-introduction letter and gain a competitive edge.

  
  

Requirements

• Since this is the process of mapping a circuit designed in a language into physical gates, the following prerequisite knowledge is required:

  • Digital Logic Circuits

  • CMOS operating principles

  • Basic knowledge of the Verilog language

  • [Inflearn Lecture] It is recommended to take the Basic Design Synthesis Training first.
    https://inf.run/XkbCP

• Linux environment

  • In practice, a Linux environment is used.

  • Unlike Windows, it is a method of communicating with the computer primarily by entering commands.

  • It is helpful to know the major commands used in Linux.

• TCL for communicating with EDA tools

  • It is an interpreted language, and most EDA tools operate through a TCL interface.

    
    

  • If you are looking to get a job in digital circuit design, it is recommended to study this in your spare time.

    
    

Reference sites for study materials related to the lecture

• TCL, the most widely used scripting language in the PI / PD fields

  • https://tcltk.co.kr