[2-Week Synthesis Practice Challenge 7th Batch] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Schedule: ~ 2026-06-15, closed after the first 5 applicants Lecture Schedule: 2026-06-16 ~ 2026-06-29 Content: Hands-on practice of the process of converting RTL-level digital circuit design code described in HDL into logic gates