inflearn logo
강의

Course

inflearn logo
Challenge
모집 마감
Hardware

/

Semiconductor

[2-Week Synthesis Practice Challenge 1st Cohort] Experience RTL Synthesis in a Real-World Environment (Synopsys Design Compiler)

Recruitment Period: December 23, 2025 (Tue) ~ January 5, 2026 (Mon) - First 5 applicants Class Schedule: January 6, 2026 (Tue) ~ January 19, 2026 (Mon) Content: Hands-on practice of converting RTL-level digital circuit design code written in HDL into logic gates

Verilog HDL
synthesis
digital-logic

17개 수업 학습

질문하고 즉시 답을 얻어요.

MetaEncore님과 함께해요!

126

Learners

14

Reviews

12

Answers

5.0

Rating

6

Courses

Market demand for application-specific integrated circuits (ASICs) such as AI (Artificial Intelligence) and IoT (Internet of Things) is increasing, and many chips are actually being designed, but it is rare for them to lead to substantial changes in our lives.

This is because many ASIC designs are either functionally flawed or fail to meet the planned performance requirements. To enrich our lives by creating high-quality semiconductors, services that provide advanced functional and performance verification capable of handling increasingly large and complex designs are essential. MetaEncore is a company that aims to increase the number of semiconductors that benefit humanity by providing such services.

More
1poster

*Must check recruitment and class schedule, must complete survey after class registration

Please check it out!

  • This course includes a 2-week license for Synopsys tools and focuses on how to use the tools.

  • Synopsys tools are generally only available to current industry professionals, but

    This opportunity to try it out yourself is provided exclusively to challenge course participants.


  • After applying, you must complete the survey to receive access to the tool.

[2-Week Compositing Practice Challenge Season 1]

Application Period: December 23, 2025, 9:00 AM ~ January 5, 2026, 5:00 PM

Class Schedule: January 6, 2026, 9:00 AM ~ January 19, 2026, 5:00 PM

*The lecture schedule and Design Compiler Tool usage rights schedule are the same.


Synthesis

What is compositing?

  • Converting Register Transfer Level Design written in HDL such as Verilog to Gate Level

  • During the conversion process, the Design is optimized according to constraints called Synopsys Design Constraint

  • Finally, mapping to the Standard cells provided by the Foundry


The Importance of Synthetic Experience

Creating a Persuasive Personal Statement

The industry prefers new hires with experience in synthesis and timing verification.
However, gaining synthesis experience requires significant cost and time.
While the industry demands experience, offline training courses also have high competition rates.
This course provides a training environment that replicates the actual working environment used in practice.
It uses Synopsys Design Compiler, the most widely used tool in the industry.
Through this course, you will be able to create a competitive resume for offline training course selection and the job market.


Korea's First Online Course on Compositing Practice

Things covered in the compositing practice lecture

  • Section 1. Preparing the Practice Environment


    • You can set up the practice environment in less than 5 minutes.

  • Section 2. Preparing the Practice Design

    • Practice reading RTL Design described in provided HDL code into the Tool

    • Practical Exercise on Checking the Read RTL Design

    • Practice Methods for Accessing Each Object

  • Section 3. Describing Synopsys Design Constraints

    • Practice Declaring Clock, the Core of Digital Circuits

    • # Modeling the External Environment of the Chip

    • Basic Timing Verification Variations and Exception Cases Practice

  • Section 4.

    • Preparation Practice for Gate Level Compilation

    • Compile Progress Practice and Comparison

    • Practice Checking Reports After Compilation

What You Gain from Compositing Practice Lectures

  • You will experience Design Compiler, which is most commonly used in practical work environments.

  • You can differentiate your resume while building competitiveness.


# Preparation

  • The process of mapping circuits designed in language to Gates with 'physical existence' requires the following prerequisite knowledge:

    • Digital Logic Circuits

    • CMOS Operating Principle

    • Basic Knowledge of the Verilog Language

    • [Inflearn Course] I recommend taking Basic Design Synthesis Training first.
      https://inf.run/xc2V3

  • Linux environment

    • In practice, Linux environments are used.

    • Unlike Windows, it's a method of communicating with the computer primarily through entering commands.

    • It's helpful to know the main commands used in Linux.

  • # Communicating with EDA Tools Using TCL

    • It is an interpreter-based language, and most EDA tools operate with a TCL interface.


    • If you want to pursue a career in digital circuit design, it's good to study whenever you have time.


Reference sites for study materials related to the course

1월

6일

챌린지 시작일

2026년 1월 6일 AM 12:00

챌린지 종료일

2026년 1월 19일 AM 08:00

챌린지 커리큘럼

All

17 lectures ∙ (3hr 7min)

챌린지에서 배워요

  • Experience real-world environments including Linux in advance

  • Experience the most widely used Synthesis Tool in the industry

  • Create a differentiated and competitive personal statement with just one experience

Recommended for
these people

Who is this course right for?

  • Job seekers

  • For those who wish to change their job to semiconductor design implementation

Need to know before starting?

  • Basic Digital Circuit Design Flow

  • # Translation Verilog HDL --- **Note**: This appears to be a technical term

  • Logic Circuit

  • [Inflearn Online Classes] Basic Design Synthesis Training (Digital Circuit Design Implementation)

Reviews

Not enough reviews.
Please write a valuable review that helps everyone!

취소 및 환불 규정
챌린지는 지식공유자가 설정한 수업 최소 정원이 충족되지 않을 경우, 폐강 안내가 고지되며 결제 내역이 자동취소됩니다.

MetaEncore's other courses

Check out other courses by the instructor!

Basic SystemVerilog Testbench (Circuit Design Verification)Course Thumbnail

Basic SystemVerilog Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, verification, system-verilog-dpi

5.0

(6)

Update
Update
Mission
Mission

You will learn the basic syntax of SystemVerilog and testbench design techniques using SystemVerilog classes. Additionally, you can experience and learn the complete basic cycle of hardware circuit design verification by utilizing VCS, an EDA Tool from Synopsys used in the industry. Related search terms SystemVerilog, SystemVerilog, SystemVerilog, Verilog, Verilog, Verilog, SOC, circuit design, circuit verification, verification, Verification, chip design, chip verification, Samsung Electronics, Hynix, new employee training, in-house training, Synopsys, VCS, semiconductor, employment, career, fabless

Basic

Basic

Verilog HDL, system-verilog, verification

Basic SystemVerilog Testbench (Circuit Design Verification)Course Thumbnail

Basic SystemVerilog Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, verification, system-verilog-dpi

5.0

(6)

Update
Update
Mission
Mission
Basic Design Synthesis Training (Digital Circuit Design Implementation)Course Thumbnail

Basic Design Synthesis Training (Digital Circuit Design Implementation)

MetaEncore

$254.10

Beginner / EDA, digital-logic, vlsi, soc, asic

5.0

(6)

Through what stages are semiconductor chips designed and manufactured? We will examine the basic concepts of logic circuits and the Chip Design Flow required for PI (Physical Implementation) / PD (Physical Design) roles step-by-step, and explore the key concepts of the synthesis process based on the tools used for digital chip circuit design in the industry.

Beginner

Beginner

EDA, digital-logic, vlsi

Basic Design Synthesis Training (Digital Circuit Design Implementation)Course Thumbnail

Basic Design Synthesis Training (Digital Circuit Design Implementation)

MetaEncore

$254.10

Beginner / EDA, digital-logic, vlsi, soc, asic

5.0

(6)

Basic UVM Testbench (Circuit Design Verification)Course Thumbnail

Basic UVM Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, uvm

New
New
Mission
Mission

Through this course, you will understand the UVM Class library and learn testbench design techniques using UVM.

Basic

Basic

Verilog HDL, system-verilog, uvm

Basic UVM Testbench (Circuit Design Verification)Course Thumbnail

Basic UVM Testbench (Circuit Design Verification)

MetaEncore

$338.80

Basic / Verilog HDL, system-verilog, uvm

New
New
Mission
Mission

$84.70