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[2-Week Synthesis Practice Challenge 1st Cohort] Experience RTL Synthesis in a Real-World Environment (Synopsys Design Compiler)
Hardware

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Semiconductor

[2-Week Synthesis Practice Challenge 1st Cohort] Experience RTL Synthesis in a Real-World Environment (Synopsys Design Compiler)

In just 2 weeks, here's what you'll get

  • Experience real-world environments including Linux in advance

  • Experience the most widely used Synthesis Tool in the industry

  • Create a differentiated and competitive personal statement with just one experience

Starts Jan 6

13 days

Finish Jan 19

MetaEncore님과 함께해요!

198

Learners

27

Reviews

37

Answers

4.7

Rating

11

Courses

Market demand for custom chips (ASIC, application-specific integrated circuits), including AI (Artificial Intelligence) and IoT (Internet of Things), is growing, and many chips are actually being designed, but few lead to tangible changes in our lives.

This is because many ASIC designs contain functional errors or fail to meet the performance requirements that were originally planned. To create good semiconductors and enrich our lives, we need services that provide advanced functional and performance verification capable of handling increasingly large and complex designs. Meta Encore is a company that aims to increase the number of semiconductors that benefit people by providing such services.

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1poster

*Must check recruitment and class schedule, must complete survey after class registration

Please check it out!

  • This course includes a 2-week license for Synopsys tools and focuses on how to use the tools.

  • Synopsys tools are generally only available to current industry professionals, but

    This opportunity to try it out yourself is provided exclusively to challenge course participants.


  • After applying, you must complete the survey to receive access to the tool.

[2-Week Compositing Practice Challenge Season 1]

Application Period: December 23, 2025, 9:00 AM ~ January 5, 2026, 5:00 PM

Class Schedule: January 6, 2026, 9:00 AM ~ January 19, 2026, 5:00 PM

*The lecture schedule and Design Compiler Tool usage rights schedule are the same.


Synthesis

What is compositing?

  • Converting Register Transfer Level Design written in HDL such as Verilog to Gate Level

  • During the conversion process, the Design is optimized according to constraints called Synopsys Design Constraint

  • Finally, mapping to the Standard cells provided by the Foundry


The Importance of Synthetic Experience

Creating a Persuasive Personal Statement

The industry prefers new hires with experience in synthesis and timing verification.
However, gaining synthesis experience requires significant cost and time.
While the industry demands experience, offline training courses also have high competition rates.
This course provides a training environment that replicates the actual working environment used in practice.
It uses Synopsys Design Compiler, the most widely used tool in the industry.
Through this course, you will be able to create a competitive resume for offline training course selection and the job market.


Korea's First Online Course on Compositing Practice

Things covered in the compositing practice lecture

  • Section 1. Preparing the Practice Environment


    • You can set up the practice environment in less than 5 minutes.

  • Section 2. Preparing the Practice Design

    • Practice reading RTL Design described in provided HDL code into the Tool

    • Practical Exercise on Checking the Read RTL Design

    • Practice Methods for Accessing Each Object

  • Section 3. Describing Synopsys Design Constraints

    • Practice Declaring Clock, the Core of Digital Circuits

    • # Modeling the External Environment of the Chip

    • Basic Timing Verification Variations and Exception Cases Practice

  • Section 4.

    • Preparation Practice for Gate Level Compilation

    • Compile Progress Practice and Comparison

    • Practice Checking Reports After Compilation

What You Gain from Compositing Practice Lectures

  • You will experience Design Compiler, which is most commonly used in practical work environments.

  • You can differentiate your resume while building competitiveness.


# Preparation

  • The process of mapping circuits designed in language to Gates with 'physical existence' requires the following prerequisite knowledge:

    • Digital Logic Circuits

    • CMOS Operating Principle

    • Basic Knowledge of the Verilog Language

    • [Inflearn Course] I recommend taking Basic Design Synthesis Training first.
      https://inf.run/xc2V3

  • Linux environment

    • In practice, Linux environments are used.

    • Unlike Windows, it's a method of communicating with the computer primarily through entering commands.

    • It's helpful to know the main commands used in Linux.

  • # Communicating with EDA Tools Using TCL

    • It is an interpreter-based language, and most EDA tools operate with a TCL interface.


    • If you want to pursue a career in digital circuit design, it's good to study whenever you have time.


Reference sites for study materials related to the course

1월

6일

챌린지 시작일

2026년 1월 6일 오전 12:00

챌린지 종료일

2026년 1월 19일 오전 08:00

챌린지 커리큘럼

All

16 lectures ∙ (3hr 4min)

Recommended for
these people

Who is this course right for?

  • Job seekers

  • For those who wish to change their job to semiconductor design implementation

Need to know before starting?

  • Basic Digital Circuit Design Flow

  • # Translation Verilog HDL --- **Note**: This appears to be a technical term

  • Logic Circuit

  • [Inflearn Online Classes] Basic Design Synthesis Training (Digital Circuit Design Implementation)

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취소 및 환불 규정
챌린지는 지식공유자가 설정한 수업 최소 정원이 충족되지 않을 경우, 폐강 안내가 고지되며 결제 내역이 자동취소됩니다.

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