Challenge
모집 마감
[2-Week Synthesis Practice Challenge 1st Cohort] Experience RTL Synthesis in a Real-World Environment (Synopsys Design Compiler)
Recruitment Period: December 23, 2025 (Tue) ~ January 5, 2026 (Mon) - First 5 applicants Class Schedule: January 6, 2026 (Tue) ~ January 19, 2026 (Mon) Content: Hands-on practice of converting RTL-level digital circuit design code written in HDL into logic gates
Verilog HDL
synthesis
digital-logic
News
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This challenge course is conducted while directly using Synopsys's Design Compiler tool.
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