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Implement LVDS (Serdes) in FPGA.
63 learners
Level Intermediate
Course period Unlimited
Lecture Update News
hello.
The Verilog FPGA Program 5 (LVDS/Serdes, HIL-A35T) lecture has been updated. Added content to implement maximum transfer speeds.
Please download the data from the data room and use it. I hope you find this lecture informative.
Thank you~!!