Hello. I am an embedded hardware circuit design engineer. (Not in the FPGA field ^^) Thank you for the great lecture. Even my seniors at work find it difficult to explain, but you explain the concepts so easily. I tried to learn Verilog HDL, but I had no opportunity to learn it while working at a small to medium-sized company. If I wanted to learn it properly, I would have to quit my job and take a 6-month to 1-year course. I was about to give up when I happened to find your lecture. Now I have hope. I am sorry, but please take care of your health and do well in the next lecture. Thank you.

eleazar42911870

Let's build AMBA AXI4 design and VIP verification experience, foundational to SoC Bus, through self-study of design with Verilog HDL!

semisgdh

Design Self-Study Flavor's Practical Verilog HDL Season 2 (Complete Mastery of AMBA AXI4)

You are in the same industry. I am glad that it was helpful, and the course review is really encouraging. I hope you take care of your health and come back with a good lecture next time. Always enjoy!

반도체

verilog

fpga

amba

임베디드

설계독학과 함께 Verilog HDL을 이용하여 SoC Bus의 기본이 되는 AMBA AXI4 설계와 VIP 검증 경험을 쌓아봅시다!

설계독학맛비

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

설계독학맛비's 실전 Verilog HDL Season 2 (AMBA AXI4 완전정복)

설계독학맛비's Verilog HDL Season2 를 시작하기 전에

Data 전송의 기본이되는 Valid / Ready Handshake 설계 정복하기

원활한 Data 전송을 위한 필수 Buffer, FIFO 설계 정복하기

AXI4 Interface 를 설계하기 위한 이론 및 검증환경 숙지하기

AXI4-Lite 설계 정복하기

AXI4-Stream 설계 정복하기

AXI4 설계 정복하기 (feat. 설계엔지니어라면 꼭 알고 있어야하는 내용들!!)

Mem copy IP. DMA (Direct Memory Access) 설계하기.

[프로젝트] "Matbi Mem copy IP" 를 FPGA 에 올려보자! (동작 및 Performance 확인)

마치며