[2-Week Synthesis Practice Challenge 4th Class] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

You will learn the basic syntax of SystemVerilog and testbench design techniques using SystemVerilog classes. Additionally, you can experience and learn the complete basic cycle of hardware circuit design verification by utilizing VCS, an EDA Tool from Synopsys used in the industry. Related search terms SystemVerilog, SystemVerilog, SystemVerilog, Verilog, Verilog, Verilog, SOC, circuit design, circuit verification, verification, Verification, chip design, chip verification, Samsung Electronics, Hynix, new employee training, in-house training, Synopsys, VCS, semiconductor, employment, career, fabless

Through what stages are semiconductor chips designed and manufactured? We will examine the basic concepts of logic circuits and the Chip Design Flow required for PI (Physical Implementation) / PD (Physical Design) roles step-by-step, and explore the key concepts of the synthesis process based on the tools used for digital chip circuit design in the industry.

Through this course, you will understand the UVM Class library and learn testbench design techniques using UVM.