[2-Week Synthesis Practice Challenge 8th Batch] Experiencing RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

[2-Week Synthesis Hands-on Challenge 8th Batch]

Recruitment Schedule: ~ 2026-08-10 5:00 PM

Lecture Schedule: 2026-08-11 9:00 AM ~ 2026-08-24 5:00 PM

*The lecture schedule and the Design Compiler Tool license schedule are the same.

Synthesis (Synthesis)

What is synthesis?

• Converting Register Transfer Level designs written in HDL such as Verilog into Gate Level

• Optimize the design according to the constraints called Synopsys Design Constraints during the conversion process.

• Finally mapping to standard cells provided by the foundry.

  
  

Importance of synthesis experience

Creating a Persuasive Self-Introduction

The industry prefers new employees with experience in synthesis and timing verification.
However, gaining experience in synthesis requires a significant amount of time and money.
While the industry demands experience, offline training courses are also highly competitive.
This course provides an educational environment that replicates the actual environment used in the field.
It uses Synopsys Design Compiler, the most widely used tool in the industry.
Through this course, you will be able to create a competitive resume for both offline training course selection and the job market.

Korea's first online synthesis practice course

What is covered in the synthesis practice course

• Section 1. Preparing the Practice Environment

  
  

  • You can set up the practice environment within 5 minutes.

• Section 2. Preparing the Practice Design

  • Practice on how to load the RTL Design described in the provided HDL code into the tool

  • Practice the process of checking the imported RTL design.

  • Practice on methods to access each object

• Section 3. Specifying Synopsys Design Constraints

  • Practice on clock declaration, the core of digital circuits

  • Chip external environment modeling practice

  • Basic timing verification variations and exceptions practice

• Section 4.

  • Preparation practice for gate-level compilation

  • Compilation practice and comparison

  • Practice on checking reports after compilation

What you gain from the synthesis practice lecture

• You will experience the real-world environment and the most widely used Design Compiler.

• You can differentiate your self-introduction and gain a competitive edge.

  
  

Requirements

• Because it is a process of mapping circuits designed in a language to gates with 'substance', the following prerequisite knowledge is required.

  • Digital Logic Circuit

  • CMOS Operating Principles

  • Basic knowledge of the Verilog language

  • [Inflearn Lecture] It is recommended to take Basic Design Synthesis Training first.
    https://inf.run/XkbCP

• Linux environment

  • In practice, a Linux environment is used.

  • Unlike Windows, it is a method of communicating with the computer primarily by entering commands.

  • It is helpful to know the key commands used in Linux.

• TCL for communicating with EDA tools

  • It is an interpreted language, and most EDA tools operate via a TCL interface.

    
    

  • If you are looking to get a job in digital circuit design, it is recommended to study it whenever you have the chance.

    
    

Reference site for study materials related to the lecture

• TCL, the most widely used scripting language in the PI / PD field

  • https://tcltk.co.kr