[2-Week Synthesis Practice Challenge 8th Batch] Experiencing RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Schedule: ~ 2026-08-10 (First-come, first-served for the first 5 people) Lecture Schedule: 2026-08-11 ~ 2026-08-24 Content: Hands-on practice of the process of converting RTL-level digital circuit design code described in HDL into logic gates.