UART is the most basic and widely utilized serial communication method, making it a very suitable learning topic for beginners new to FPGA design. In this course, we will thoroughly understand the communication principles and frame structure of UART, and based on this, we will proceed with directly implementing transmit/receive logic through RTL (Register Transfer Level) design. By implementing UART on an FPGA, you can systematically develop your digital circuit design skills and gain experience verifying its operation at the actual hardware level through simulation and verification. Furthermore, by learning the method utilizing the MicroBlaze soft processor and Xilinx UART IP, you will gain a broad understanding of processor-based system design flow and interface configuration. This will enable you to acquire comprehensive development capabilities encompassing both logic design and processor design.

In this lecture, we will understand the basic concepts and operating principles of FPGAs, and examine the advantages of FPGAs and their differences from ASICs. Next, we will explain the FPGA design process and detailed FPGA design areas. We will learn about the types and roles of FPGA development tools, and proceed with the installation of Vivado, an AMD FPGA development tool. Through a simple example design practical exercise, you will experience the FPGA design process.

This course introduces how to design a Gigabit Ethernet communication system using AMD FPGAs and TEMAC IP. In Vivado, we will generate and configure the TEMAC IP, connect it to the Top module, and design a hardware system capable of transmitting and receiving Ethernet frames at 1Gbps speed. We will also learn the basic concepts of the Ethernet protocol, frame structure, and debugging methods (ILA, Wireshark, etc.). We will design the ARP response and UDP transmission RTL and measure performance on a PC.