Learning RISC-V Architecture Through Debugging - Part 2

1. To commemorate the launch of Korea's first RISC-V course, we are issuing a 30% discount coupon (first come, first served for 100 people).

Coupon link: https://inf.run/C7qRb

2. 2025 Latest Course Renewal

I've discovered useful content about the latest RISC-V architecture features that can be directly applied to real-world projects, and have added the following lectures.

• Added 'Synchronous Exception Operation' session (4 lectures) - 07/23 (2025)

Emerging in the latest system software industry
RISC-V Architecture

Recently, RISC-V architecture, an open source-based CPU architecture, has been emerging. If you look at IT-related press articles and news, you can immediately see the following:

• Big tech companies such as nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startup companies designing various chips using RISC-V is increasing domestically, and the proportion of developing RISC-V device-based products is growing.

• When designing AI semiconductors, RISC-V-based CPU architectures are widely utilized.

• By 2026, 15 billion devices are expected to be released based on RISC-V.

• In graduate schools (processor design), various research is being conducted using toolkits that can design RISC-V CPUs.

Embedded and system software companies are increasingly developing products utilizing the RISC-V CPU architecture. As a result, job seekers need to prepare for RISC-V in technical interviews as well.

Background of Creating This Course

For beginners, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what's important among the vast amount of content that makes up RISC-V

• I don't know which features among the components that make up RISC-V are actually used in real-world projects

• Even if you read the RISC-V specification documents diligently, they are difficult to understand right away

  
  

• It's difficult to understand what the terms used to explain RISC-V actually mean

  
  

The reality is that compared to the Arm architecture, there are not enough resources related to the RISC-V architecture, and there is a lack of materials that explain RISC-V in a concrete and easy-to-understand way. This course was created to address the difficulties that system software developers, including junior developers, experience in the process of learning RISC-V.

Course Structure and Roadmap for Parts 1 and 3

This lecture covers the content of Part 2, which focuses on the core features of RISC-V, from the complete RISC-V lecture series.

• Part 1: RISC-V Introduction, Registers, Assembly Instructions, Privilege Mode (Learning RISC-V Architecture through Debugging Part 1)

• Part 2: Exceptions (Memory Abort Exception), Interrupts, PLIC (Platform-level Interrupt Controller), Calling convention

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension (Learning RISC-V Architecture through Debugging Part 3)

  
  

You can find the complete RISC-V architecture course in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key Differentiating Points of the Course

Here's what you'll learn 📕

The basic concepts of exceptions are explained in detail, and the key features defined in the RISC-V architecture are explained in an easy-to-understand manner.

It explains the execution flow of exceptions, a core feature of the RISC-V architecture. It also provides a detailed explanation of how exceptions are handled in systems consisting of machine mode and user mode.

Explains the exception codes defined in the RISC-V architecture that indicate the cause of an exception, and also describes the flow of how exceptions are handled for memory aborts.

From a software development perspective, it provides a detailed explanation of the execution flow when exceptions and crashes occur.

We analyze the assembly instructions line by line and explain the flow of how exceptions are triggered. We also explain how exceptions are handled in the stack when they occur.

We will practice exceptions by executing assembly instructions using the T32 debugging practice program. We will explain in detail which CSR (scause, mcause) registers are modified when an exception is triggered.

While practicing triggering exceptions with the TRACE32 program, we will explain in detail the exception handlers processed in the Linux kernel.

While analyzing memory dumps received from RISC-V based boards, we explain how exceptions work in the RISC-V architecture: analyzing kernel logs and call stacks.

We will conduct a hands-on debugging session on page tables using the TRACE32 program. Through this, we will specifically identify the cause that triggered the exception.

Explains the basic operation of interrupt controllers defined in the RISC-V architecture. Provides an easy-to-understand explanation of the structure of PLIC and CLIC.

Review the exception code related to interrupts and explain the structure of the PLIC (Platform Level Interrupt Controller).

Explains the core hardware components that make up the PLIC and provides an easy-to-understand explanation of the CSR registers that control the PLIC.

This section explains the Calling Convention introduced in the RISC-V architecture and reviews the registers that support the Calling Convention.

I'll explain the big picture of how arguments passed to functions are handled.

We analyze assembly instructions that support the Calling convention in RISC-V architecture. We also analyze example assembly instructions - c.sdsp instruction analysis

Analyzing assembly instructions that support the Calling convention of the RISC-V architecture. Also analyzing example assembly instructions - c.ldsp instruction analysis

Analyze assembly instructions that support the Calling convention of the RISC-V architecture. Also analyze example assembly instructions - c.ldsp instruction analysis

Through TRACE32 debugging practice, we will restore a corrupted call stack.

Through TRACE32 debugging practice, we will analyze memory dumps caused by stack overflow.

Based on book writing/teaching experience,
deeper and more detailed than anyone else!

In the field of system software in Korea, unprecedented! An author who wrote books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books selected as excellent books by the National Academy of Sciences of the Republic of Korea), and the first in Korea to publish "Reverse Engineering Armv8-A Systems" (in English) through an international publisher (Packt), a global author. Above all, a current industry developer who best understands the latest system software trends (electric vehicles, system semiconductors - system software). Also an educator who is most actively engaged in knowledge dissemination activities in the system software field.

• 'Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis' author (Packt Publishing)

• Author of 'Arm Architecture Structure and Principles for System Software Development' (2024 National Academy of Sciences Outstanding Book Award)

• Author of 'Learning Linux Kernel Structure and Principles through Debugging' (2021 National Academy of Sciences Outstanding Book Award)

• Main instructor for 'Programmers Dev Course: Linux System and Kernel Expert'

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Mastering the Linux Kernel with ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' in-house instructor (domestic and international developers included) - (2020~2024)