Hello, this is Sam Coach.
I'm writing this because I have some news I'd like to share first with those who have taken the course.
View the Analog Circuit Design Fundamentals Training
It started in the Q&A forum.
Since uploading the lecture, I have been replying to the posts you left on the questions board.
I only increased L, but the gain isn’t what I expected.
The slew rate is coming out absurdly large.
The PSRR is less than 10 dB.
How do you determine the specifications initially?
I could have written down the cause in a reply. But I always felt something was missing while writing it.
To understand why that number came out, I need to run the circuit again and verify it with my own eyes, but I couldn’t provide that experience in a reply.
Lab 1 · This is a screen showing the operating point run in xschem displayed directly on the schematic. Read gm and id on the circuit instead of transferring them to a table.
It was the same when designing analog IP at the company. If the hand-calculated values differed from the simulation results, we did not move on to the next step until we found out where the difference came from.
Before moving past a block, I ran both corners and Monte Carlo to fill out the spec table, and a colleague reran the table. In the lecture, I showed you this process on my screen, but it’s something you need to try a few times yourself to get used to.
So this time, instead of using my screen, I created a hands-on exercise that you can run on your own PC. It is analog circuit design fundamentals training.
How is it different from the lectures?
In the lectures so far, we mainly used LTspice with the TSMC 180 nm library. In this lab, we switched to xschem, ngspice, and sky130.
This is the screen showing the Lab 15 · 2-stage OPAMP loop testbench opened in xschem. It was drawn using sky130’s nfet_01v8 · pfet_01v8.
They are all open source, so anyone can install them without a license. sky130 is a PDK for an actual process that has been made public, so it includes corner models and Monte Carlo models, and it also has design rules, allowing you to view the layout at its actual size.
This is a KLayout screen showing the same OPAMP drawn according to the sky130 design rules. The large rectangle on the right is the compensation capacitor Cc.
I also run the 45 corners and Monte Carlo on my PC.
Lab 17 · This is an ngspice screen showing 1,000 Monte Carlo runs of the offset caused by mismatch in the input pair. Each dot represents one run.
For those who will be using Virtuoso · ADE at a company, I have also included a guide showing side by side where to perform the same tasks in Cadence.
A lab proceeds as follows.
The sequence is the same for every lab. First, predict and write down the result, then run it, and see how accurate your prediction was.
This is the first question in Lab 1. If Vds is increased fourfold from 0.3 V to 1.2 V, by what percentage will Id increase? Before looking at the answer, write down your number first.
Once a prediction is saved, it cannot be changed. The incorrect number needs to remain so that you’ll look for where you went wrong.
The questions listed above are also included in the lab.
A circuit with only L increased is run again in Lab 5.
What determines the slew rate is covered in Lab 15.
How to write and simulate PSRR is covered in Lab 19.
In the spec, we go through the process of determining W and current from scratch for the first time in Lab 9.
Starting with a single transistor, you will design a CS amp, differential pair, current mirror, and eventually a 2-stage OPAMP. The final step is a design review, where you run through a block handed over by a colleague again according to the checklist. There are four Levels and 23 Labs.
At the end of each Level, there is a Level check. You receive a spec you’ve never seen before, determine W · L · current, and the check script grades each spec item. If you take it again, a new spec appears. It’s designed so that you can’t pass by memorizing the answers.
After completing Level 3, you will move on to a set of Project Prep exercises where you run the blocks used in SAR ADCs, PLLs, and DC-DC converters at the transistor level.
This is the KLayout screen showing the CDAC, comparator, and switch of the SAR ADC core in Project prep 1, drawn according to sky130 design rules.
You can try it for free before making a payment.
The first three screens are free as long as you sign up and log in.
Start check · Install the tools on your PC and check whether the baseline numbers come out correctly.
Lab 1 · Run a transistor and read the operating point on the schematic
Simulation guide · A glossary of ngspice commands and error messages used in the lab
This is a region diagram for Lab 1. It shows on a single page which region the transistor is in according to Vgs and Vds. Lab 1 is free, so you can move this diagram around yourself.
A Windows 10 · 11 PC with at least 30 GB of disk space and 8 GB of memory is required. Check whether it works on your PC first with Start check.
If the tool stops during practice or displays different numbers, please ask through the “Contact Us” link provided at each step. The specific Lab and step will be attached automatically, so you don’t need to explain the situation from the beginning.
You can view the structure and actual screens here.
View the Analog Circuit Design Fundamentals Training
I’m also creating the fundamentals for Digital · Layout · Verification · Implementation · HW board · Embedded in the same way. I’ll let you know again each time one is opened.
Thanks to those who left questions, I was able to understand what I should create as hands-on exercises. Thank you. I’ll continue checking the Q&A board in the future.
Sincerely, Coach Sam